0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs

スポンサーリンク

概要

論文の詳細を見る
2012-04-01

著者

関連論文

Adaptive Circuits for the 0.5-V Nanoscale CMOS Era
Long-Retention-Time, High-Speed DRAM Array with 12-F^2 Twin Cell for Sub 1-V Operation(Memory,Low-Power, High-Speed LSIs and Related Technologies)
FOREWORD (Special Issue on ULSI Memory Technology)
Sub 1V Swing Internal Bus Architecture for Future Low-Power ULSI's (Special Section on the 1992 VLSI Circuits Symposium)
The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
Eliminating the Threshold-Voltage Offset of p-Channel Metal-Oxide-Semiconductor Field Effect Transistors in High-Density Dynamic Random Access Memory
An Independent-Source Overdriven Sense Amplifier for Multi-Gigabit DRAM Array
Resistive Switching Ion-Plug Memory for 32-nm Technology Node and Beyond
Eliminating the Threshold-Voltage Offset of p-Channel Metal-Oxide-Semiconductor Field Effect Transistors in High-Density Dynamic Random Access Memory
A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs
A Low-V_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays
Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device

もっと見る

スポンサーリンク