The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips

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概要

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• The advantages of a neuro-chip architecture based on a DRAM are demonstrated through a discussion of the general issues regarding a memory based neuro-chip architecture and a comparison with a chip based on an SRAM. The performance of both chips is compared assuming digital operation, a .5-V supply voltage, a 10^6-synapse neural network capability, and a 0.5-μm CMOS design rule. The use of a one-transistor DRAM cell array for the storage of synapse weights results in a chip 55% smaller than an SRAM based chip with the same 8-Mbit memory capacity and the same number of processing elements. No additional operations for refreshing the DRAM cell array are necessary during the processing of the neural networks. This is because all the synapse weights in the array are transferred to the processing elements during the processing and the DRAM cells in the array are automatically refreshed when they are selected. The precharge operation of the DRAM cell array degrades the processing speed, however a processing speed of 1.37 GCPS is expected for the DRAM based chip. That speed is comparable to the 1.71 GCPS for the SRAM based chip with the same 256 parallel-processing elements. A DRAM cell array has the additional advantage of lower power dissipation in this specific usage for the neuro-chip. The dynamic operation of the DRAM cell array results in a 10% lower operating power dissipation than a chip using an SRAM cell array at the same processing speed of .37 GCPS. That lower operating power dissipation enables a DRAM based chip to run on a 1.5-V dry cell for longer under intermittent daily use even though the SRAM cell array has little power dissipation in data-holding mode.

• 社団法人電子情報通信学会の論文
• 1993-07-25

著者

• Sakata Takeshi

  Central Research Laboratory Hitachi Ltd.

• Sakata Takeshi

  Central Research Lab. Hitachi Ltd.

• WATANABE Takao

  Central Research Laboratory, Hitachi Ltd.

• Kimura Katsutaka

  Central Research Laboratory, Hitachi, Ltd.

• ITOH Kiyoo

  Central Research Laboratory, Hitachi, Ltd.

• Itoh Kiyoo

  Central Research Lab. Hitachi Ltd.

• Aoki Masakazu

  Central Research Laboratory, Hitachi Ltd.

• Kimura Katsutaka

  Central Research Lab. Hitachi Ltd.

• Aoki Masakazu

  Central Research Lab. Hitachi Ltd.

• Watanabe Takao

  Central Research Lab. Hitachi Ltd.

関連論文

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• Adaptive Circuits for the 0.5-V Nanoscale CMOS Era
• A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
• Programming and Program-Verification Methods for Low-Voltage Flash Memories Using a Sector Programming Scheme
• A High-Endurance Read/Write Scheme for Half-V_cc Plate Nonvolatile DRAMs with Ferroelectric Capacitors(Special Issue on Nonvolatile Memories)
• Amorphous Channel SESO Memory with Good Logic Process Compatibility for Low-power High-density Embedded RAM
• High-Reliability Programming Method Suitable for Flash Memories of More Than 256Mb
• Long-Retention-Time, High-Speed DRAM Array with 12-F^2 Twin Cell for Sub 1-V Operation(Memory,Low-Power, High-Speed LSIs and Related Technologies)
• Dynamic Terminations for Low-Power High-Speed Chip Interconnection in Portable Equipment
• The Umbrella Cell : A High-Density 2T Cell for SOC Applications(Memory, Low-Power LSI and Low-Power IP)
• FOREWORD (Special Issue on ULSI Memory Technology)
• Sub 1V Swing Internal Bus Architecture for Future Low-Power ULSI's (Special Section on the 1992 VLSI Circuits Symposium)
• A Robust Array Architecture for a Capacitorless MISS Tunnel-Diode Memory(Integrated Electronics)
• The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
• 3-D CG Media Chip : An Experimental Single-Chip Architecture for Three-Dimensional Computer Graphics (Special Issue on Multimedia, Analog and Processing LSIs)
• An Independent-Source Overdriven Sense Amplifier for Multi-Gigabit DRAM Array
• Suppression of Hole Injection into the Tunnel Oxides of Flash Memories
• A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
• 0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs
• A Low-V_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
• Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays

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