A High-Endurance Read/Write Scheme for Half-V_cc Plate Nonvolatile DRAMs with Ferroelectric Capacitors(Special Issue on Nonvolatile Memories)
スポンサーリンク
概要
- 論文の詳細を見る
A small data-line-swing read/write scheme is described for half-V_cc plate nonvolatile DRAMs with ferroelectric capacitors designed to achieve high reliability for read/write operations. In this scheme, the normal read/write operation holds the data as a charge with a small data-line-swing, and the store operation provides sufficient polarization with a full data-line-swing. This scheme enables high read/write endurance, because the small data-line-swing reduces the fatigue of the ferroelectric capacitor. Two circuit technologies are used in this scheme to increase the operating margin. The first is a plate voltage control technique that solves the polarization retention problem of half-V_cc plate nonvolatile DRAM technologies. The second is a doubled data-line-capacitance recall technique that connects two data lines to a cell and enlarges the readout signal compared to normal operation, when only one data line is connected to a cell. These techniques and circuits improve the write-cycle endurance by almost three orders of magnitude, while reducing the array power consumption during read/write operations to one-third that of conventional nonvolatile DRAMs.
- 社団法人電子情報通信学会の論文
- 2001-06-01
著者
-
Sakata Takeshi
Central Research Laboratory Hitachi Ltd.
-
Sakata Takeshi
Central Research Lab. Hitachi Ltd.
-
TORII Kazuyoshi
Central Research Laboratory, Hitachi, Ltd.
-
Kimura Katsutaka
Central Research Laboratory, Hitachi, Ltd.
-
Torii K
Central Research Laboratory Hitachi Ltd.
-
Torii Kazuyoshi
Central Research Laboratory Hitachi Lid.
-
Torii K
Semiconductor Leading Edge Technol. Inc. Tsukuba-shi Jpn
-
FUJISAWA Hiroki
the Development Div., Elpida Memory Inc.
-
SEKIGUCHI Tomonori
Central Research Laboratory, Hitachi, Ltd.
-
KAJIGAYA Kazuhiko
the Development Div., Elpida Memory Inc.
-
Fujisawa Hiroki
The Development Div. Elpida Memory Inc.
-
Kimura Katsutaka
Central Research Lab. Hitachi Ltd.
-
Sakata T
Hitachi Ltd. Kokubunji‐shi Jpn
-
Sekiguchi T
Central Research Laboratory Hitachi Ltd.
-
Kajigaya Kazuhiko
The Development Div. Elpida Memory Inc.
-
Sekiguchi Tomonori
Central Research Laboratory Hitachi Ltd.
関連論文
- Strain-Imaging Observation of Pb(Zr, Ti)O_3 Thin Films
- Strain Imaging of Lead-Zirconate-Titanate Thin Film by Tunneling Acoustic Microscopy
- Effect of Purge Time on the Properties of HfO_2 Films Prepared by Atomic Layer Deposition(High-κ Gate Dielectrics)
- Electro-Luminescence from Ultra-Thin Silicon
- A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
- Programming and Program-Verification Methods for Low-Voltage Flash Memories Using a Sector Programming Scheme
- Inversion Electron Mobility Affected by Phase Separation in High-Permittivity Gate Dielectrics
- Dielectric Properties of RF-Magnetron-Sputtered (Ba, Pb)(Zr, Ti)O_3 Thin Films
- Single-Target Sputtering Process for Lead Zirconate Titanate Thin Films with Precise Composition Control
- A High-Endurance Read/Write Scheme for Half-V_cc Plate Nonvolatile DRAMs with Ferroelectric Capacitors(Special Issue on Nonvolatile Memories)
- A TiO2 Gate Insulator of a 1-nm Equivalent Oxide Thickness Deposited by Electron-Beam Evaporation
- Effective Electron Mobility Reduced by Remote Charge Scattering in High-K Gate Stacks : Short Note
- Highly Oxidation-Resistant TiN Barrier Layers for Ferroelectric Capacitors
- Hydrogen-related Degradation and Recovery Phenomena in Pb(Zr,Ti)O_3 Capacitors with a Platinum Electrode
- Highly Oxidation-Resistant TiN Barrier Layers for Ferroelectric Capacitors
- High-Reliability Programming Method Suitable for Flash Memories of More Than 256Mb
- Long-Retention-Time, High-Speed DRAM Array with 12-F^2 Twin Cell for Sub 1-V Operation(Memory,Low-Power, High-Speed LSIs and Related Technologies)
- Dynamic Terminations for Low-Power High-Speed Chip Interconnection in Portable Equipment
- A Robust Array Architecture for a Capacitorless MISS Tunnel-Diode Memory(Integrated Electronics)
- The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
- A Novel Laser Annealing Process for Advanced CMOS with Suppressed Gate Depletion and Ultra-shallow Junctions
- Bending Loss Characteristics of MQW Optical Waveguides (Special Issue on Optical Interconnection)
- Relationship between Barrier Thickness and Crystal Quality in InGaAs/InGaAsP Strained Multi-Quantum Well Structure
- Metal Schottky Source/Drain Technology for Ultrathin Silicon-on-Thin-Box Metal Oxide Semiconductor Field Effect Transistors
- Highly Accurate Composition Analysis of (Pb, Zr)TiO_3 Using a Scanning Electron Microscope/Energy Dispersive X-Ray Spectrometer
- An Independent-Source Overdriven Sense Amplifier for Multi-Gigabit DRAM Array
- Suppression of Hole Injection into the Tunnel Oxides of Flash Memories
- Electro-Luminescence from Ultra-Thin Silicon
- Preparation of Lead Zirconate Titanate Thin Films by Reactive Evaporation ( FERROELECTRIC MATERIALS AND THEIR APPLICATIONS)
- Effects of Thin Film Interference on Junction Activation during Sub-Millisecond Annealing
- Novel Laser Annealing Process for Advanced Complementary Metal Oxide Semiconductor Devices with Suppressed Polycrystalline Silicon Gate Depletion and Ultra shallow Junctions
- Electron Trap Characteristics of Silicon Rich Silicon Nitride Thin Films
- Investigation of Relationship between Interface State and Random Telegraph Noise Using Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated on Si(100), (110), and (111) Substrates
- Low-Shrinkage Spin-On Glass for Low Parasitic Capacitance Gap-Filling Process in Advanced Memory Devices
- Self-Aligned Fabrication Process of Electrode for Organic Thin-Film Transistors on Flexible Substrate Using Photosensitive Self-Assembled Monolayers
- Inversion Electron Mobility Affected by Phase Separation in High-Permittivity Gate Dielectrics
- State Transition of a Defect Causing Random-Telegraph-Noise Fluctuation in Stress-Induced Leakage Current of Thin SiO
- State Transition of a Defect Causing Random-Telegraph-Noise Fluctuation in Stress-Induced Leakage Current of Thin SiO₂ Films in a Metal-Oxide-Silicon Structure