Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays
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概要
- 論文の詳細を見る
- 2012-04-01
著者
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TAKEMURA Riichiro
Central Research Laboratory, Hitachi, Ltd.
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Itoh Kiyoo
Hitachi Ltd. Kokubunji‐shi Jpn
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Itoh Kiyoo
Central Research Lab. Hitachi Ltd.
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Takemura Riichiro
Central Research Laboratory Hitachi Ltd.
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Sekiguchi Tomonori
Hitachi Europe Ltd.
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Yanagawa Yoshimitsu
Central Research Laboratory Hitachi Ltd.
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KOTABE Akira
Central Research Laboratory, Hitachi, Ltd.
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Kotabe Akira
Central Research Laboratory Hitachi Ltd.
関連論文
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- FOREWORD (Special Issue on ULSI Memory Technology)
- Sub 1V Swing Internal Bus Architecture for Future Low-Power ULSI's (Special Section on the 1992 VLSI Circuits Symposium)
- The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
- Eliminating the Threshold-Voltage Offset of p-Channel Metal-Oxide-Semiconductor Field Effect Transistors in High-Density Dynamic Random Access Memory
- An Independent-Source Overdriven Sense Amplifier for Multi-Gigabit DRAM Array
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- Eliminating the Threshold-Voltage Offset of p-Channel Metal-Oxide-Semiconductor Field Effect Transistors in High-Density Dynamic Random Access Memory
- A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
- 0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs
- A Low-V_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
- Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays
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