TAKEMURA Riichiro | Central Research Laboratory, Hitachi, Ltd.

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著作論文

Long-Retention-Time, High-Speed DRAM Array with 12-F^2 Twin Cell for Sub 1-V Operation(Memory,Low-Power, High-Speed LSIs and Related Technologies)
Eliminating the Threshold-Voltage Offset of p-Channel Metal-Oxide-Semiconductor Field Effect Transistors in High-Density Dynamic Random Access Memory
An Independent-Source Overdriven Sense Amplifier for Multi-Gigabit DRAM Array
A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs
A Low-V_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays
Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device

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