ASAKURA Hisao | Information & Control Systems Division, Computer Systems Quality Assurance Section, Hitachi, Ltd.
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概要
- 同名の論文著者
- Information & Control Systems Division, Computer Systems Quality Assurance Section, Hitachi, Ltd.の論文著者
関連著者
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NAGAI Ryo
Advanced Device Development Gr., Elpida Memory, Inc.
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YAMADA Satoru
Advanced Device Development Gr., Elpida Memory, Inc.
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ASAKURA Hisao
Information & Control Systems Division, Computer Systems Quality Assurance Section, Hitachi, Ltd.
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Kimura Shunji
Ntt Network Innovation Laboratories
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TAKEMURA Riichiro
Central Research Laboratory, Hitachi, Ltd.
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MATSUOKA Hideyuki
Central Research Laboratory, Hitachi, Ltd.
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TAKAURA Norikatsu
Central Research Laboratory, Hitachi, Ltd.
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Matsuoka Hideyuki
Central Research Laboratory Hitachi Ltd.
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Takemura Riichiro
Central Research Laboratory Hitachi Ltd.
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Takaura Norikatsu
Central Research Laboratory Hitachi. Ltd.
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Matsuoka Hideyuki
Central Research Laboratory, Hitachi, Ltd., 1-280 Higashi-Koigakubo, Kokubunji, Tokyo 185-8601, Japan
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Nagai Ryo
Advanced Device Development Gr., Elpida Memory, Inc. 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
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Takemura Riichiro
Central Research Laboratory, Hitachi, Ltd., 1-280 Higashi-Koigakubo, Kokubunji, Tokyo 185-8601, Japan
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Asakura Hisao
Information & Control Systems Division, Computer Systems Quality Assurance Section, Hitachi, Ltd., Hitachi System Plaza Shinkawasaki, 890 Komukai Kashimada, Saiwai, Kawasaki, Kanagawa 212-8567, Japan
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Yamada Satoru
Advanced Device Development Gr., Elpida Memory, Inc. 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
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Takaura Norikatsu
Central Research Laboratory, Hitachi, Ltd., 1-280 Higashi-Koigakubo, Kokubunji, Tokyo 185-8601, Japan
著作論文
- Eliminating the Threshold-Voltage Offset of p-Channel Metal-Oxide-Semiconductor Field Effect Transistors in High-Density Dynamic Random Access Memory
- Eliminating the Threshold-Voltage Offset of p-Channel Metal-Oxide-Semiconductor Field Effect Transistors in High-Density Dynamic Random Access Memory