A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing

スポンサーリンク

概要

• 論文の詳細を見る

• A gated sense amplifier (GSA) consisting of a low-Vt gated preamplifier (LGA) and a high-Vt sense amplifier (SA) is proposed. The gating scheme of the LGA enables quick amplification of an initial cell signal voltage (vS0) because of its low Vt and prevents the cell signal from degrading due to interference noise between data lines. As for a conventional sense amplifier (CSA), this new type of noise causes sensing error, and the noise-generation mechanism was clarified for the first time by analysis of vS0. The high-Vt SA holds the amplified signal and keeps subthreshold current low. Moreover, the gating scheme of the low-Vt MOSFETs in the LGA drives the I/O line quickly. The GSA thus simultaneously achieves fast sensing, low-leakage data holding, and fast I/O driving, even for sub-1-V mid-point sensing. The GSA is promising for future sub-1-V gigabit dynamic random-access memory (DRAM) because of reduced variations in the threshold voltage of MOSFETs; thus, the offset voltage of the LGA is reduced. The effectiveness of the GSA was verified with a 70-nm 512-Mbit DRAM chip. It demonstrated row access time (tRCD) of 16.4ns and read access (tAA) of 14.3ns at array voltage of 0.9V.

著者

• TAKEMURA Riichiro

  Central Research Laboratory, Hitachi, Ltd.

• Itoh Kiyoo

  Central Research Lab. Hitachi Ltd.

• Akiyama Satoru

  Central Research Laboratory Hitachi Ltd.

• Takemura Riichiro

  Central Research Laboratory Hitachi Ltd.

• Sekiguchi Tomonori

  Hitachi Europe Ltd.

• Kotabe Akira

  Central Research Laboratory Hitachi Ltd.

関連論文

• Adaptive Circuits for the 0.5-V Nanoscale CMOS Era
• Long-Retention-Time, High-Speed DRAM Array with 12-F^2 Twin Cell for Sub 1-V Operation(Memory,Low-Power, High-Speed LSIs and Related Technologies)
• The Umbrella Cell : A High-Density 2T Cell for SOC Applications(Memory, Low-Power LSI and Low-Power IP)
• FOREWORD (Special Issue on ULSI Memory Technology)
• Sub 1V Swing Internal Bus Architecture for Future Low-Power ULSI's (Special Section on the 1992 VLSI Circuits Symposium)
• The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
• Eliminating the Threshold-Voltage Offset of p-Channel Metal-Oxide-Semiconductor Field Effect Transistors in High-Density Dynamic Random Access Memory
• An Independent-Source Overdriven Sense Amplifier for Multi-Gigabit DRAM Array
• Resistive Switching Ion-Plug Memory for 32-nm Technology Node and Beyond
• Eliminating the Threshold-Voltage Offset of p-Channel Metal-Oxide-Semiconductor Field Effect Transistors in High-Density Dynamic Random Access Memory
• A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
• 0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs
• A Low-V_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
• Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays
• Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device

もっと見る 閉じる

スポンサーリンク