FOREWORD (Special Issue on ULSI Memory Technology)

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概要

• 論文の詳細を見る
• 社団法人電子情報通信学会の論文
• 1996-06-25

著者

• ITOH Kiyoo

  Central Research Laboratory, Hitachi, Ltd.

• Itoh Kiyoo

  Central Research Laboratory Hitachi Ltd.

• Itoh Kiyoo

  Central Research Lab. Hitachi Ltd.

関連論文

• Adaptive Circuits for the 0.5-V Nanoscale CMOS Era
• Long-Retention-Time, High-Speed DRAM Array with 12-F^2 Twin Cell for Sub 1-V Operation(Memory,Low-Power, High-Speed LSIs and Related Technologies)
• FOREWORD (Special Issue on ULSI Memory Technology)
• Sub 1V Swing Internal Bus Architecture for Future Low-Power ULSI's (Special Section on the 1992 VLSI Circuits Symposium)
• The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
• A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
• 0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs
• A Low-V_t Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing
• Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays

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