Surface-Reaction-Controlled Tungsten CVD Technology for 0.1-µm Low-Resistive, Encroachment-Free CMOS-FET Applications
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概要
- 論文の詳細を見る
A reliable and manufacturable tungsten (W) stacked source/drain (S/D)-and-gate technology has been developed which is applicable to conventional 0.1 µm complementary metal-oxide-semiconductor field-effect transistors (CMOS-FETs). A low-resistive (2–3 Ω/sq.) and encroachment-free S/D has been achieved. This technology has overcome two major problems in the selective chemical vapor deposition (CVD) of W. First, the difference in the thickness of W films grown on p+ and n+ silicon (Si) is reduced by Si-light-etching treatment. Second, encroachment during W-CVD is suppressed by a tungsten hexafluoride (WF6) high-pressure process. Excellent electrical characteristics have been obtained in 0.1 µm CMOS-FETs using the W stacked S/D-and-gate technology.
- INSTITUTE OF PURE AND APPLIED PHYSICSの論文
- 1996-02-28
著者
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Kobayashi Nobuyoshi
Semiconductor Development Center Semiconductor & Integrated Circuits Division Hitachi Ltd.
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Kobayashi Nobuyoshi
Semiconductor & Integrated Circuits Div. Hitachi Ltd.
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NAGAI Ryo
Semiconductor & Integrated Circuits Div., Hitachi, Ltd.
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Hisamoto D
Central Research Laboratory Hitachi Ltd.
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Hisamoto Digh
Central Research Laboratory Hitachi Ltd.
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Kobayashi N
Semiconductor Development Center Semiconductor & Integrated Circuits Division Hitachi Ltd.
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Umeda Kazunori
Institute Of Mechanical Systems Engineering National Institute Of Advanced Industrial Science And Te
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Umeda Kazunori
Central Research Laboratory Hitachi Ltd.
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Nagai Ryo
Semiconductor Development Center Semiconductor & Integrated Circuits Division Hitachi Ltd.
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Nakamura Yoshitaka
Semiconductor Development Center, Semiconductor & Integrated Circuits Division, Hitachi, Ltd.,
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Nakamura Yoshitaka
Semiconductor Development Center Semiconductor & Integrated Circuits Division Hitachi Ltd.
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