Novel via Chain Structure for Failure Analysis at 65 nm-Node Fixing OPC Using Inner and Outer via Chain Dummy Patterns(<Special Section>Microelectronic Test Structures)
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概要
- 論文の詳細を見る
A novel via chain structure for failure analysis at 65 nm-node fixing OPC using inner and outer via chain dummy patterns has been proposed. The inner dummy is necessary to localize failure site in 200 nm pitch via chain using an optical beam induced resistance change method. The outer dummy protects via chain pattern from local flare and optical proximity effects. Using this test structure, we can identify the failure point in the 1.2 k and 15 k via chain fabricated by Cu/low-k single damascene process. This test structure is beneficial in the application to the 65 nm-node technologies and beyond.
- 社団法人電子情報通信学会の論文
- 2005-05-01
著者
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Kobayashi Hiromasa
Semiconductor Leading Edge Technology Inc.
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Kobayashi Nobuyoshi
Semiconductor Leading Edge Technologies Inc. (selete)
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Kobayashi Nobuyoshi
Semiconductor & Integrated Circuits Div. Hitachi Ltd.
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Kobayashi Nobuyoshi
Semiconductor Leading Edge Technology Inc.
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SODA Eiichi
Semiconductor Leading Edge Technologies Inc. (Selete)
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Soda Eiichi
Semiconductor Leading Edge Technology Inc.
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Soda Eiichi
Semiconductor Leading Edge Technologies Inc.
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MATSUBARA Yoshihisa
Semiconductor Leading Edge Technologies, Inc.
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Wakamiya Wataru
Semiconductor Leading Edge Technology Inc.
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NASUNO Takashi
Semiconductor Leading Edge Technology, Inc.
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MINAMI Akiyuki
Semiconductor Leading Edge Technology, Inc.
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TSUDA Hiroshi
Semiconductor Leading Edge Technology, Inc.
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TSUJITA Koichiro
Semiconductor Leading Edge Technology, Inc.
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Minami Akiyuki
Semiconductor Leading Edge Technology Inc.
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Nasuno Takashi
Semiconductor Leading Edge Technology Inc.
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Tsujita Koichiro
Semiconductor Leading Edge Technology Inc.
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Matsubara Yoshihisa
Semiconductor Leading Edge Technology Inc.
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Tsuda Hiroshi
Semiconductor Leading Edge Technology Inc.
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