Novel Laser Annealing Process for Advanced Complementary Metal Oxide Semiconductor Devices with Suppressed Polycrystalline Silicon Gate Depletion and Ultra shallow Junctions

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概要

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• One of the major challenges in advanced complementary metal oxide semiconductor (CMOS) technology is to achieve an adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. We investigated gate pre annealing by laser thermal process (LTP) in conjunction with laser spike annealing (LSA) source/drain (S/D) activation to effectively suppress poly-Si gate depletion while forming highly activated ultra shallow junctions for S/D. We found that carrier concentration at the poly-Si gate/gate oxide interface increases and, accordingly, electrical inversion oxide thickness ($T_{\text{inv}}$) decreases whereas dopant penetration into the Si substrate is suppressed to a level far below that in conventional rapid thermal annealing (RTA). We realized improved device performance characteristics such as a high drive current, a small threshold voltage ($V_{\text{th}}$) shift, and a reduced off current ($I_{\text{off}}$).

• 2007-04-30

著者

• Torii Kazuyoshi

  Central Research Laboratory Hitachi Lid.

• Mine Toshiyuki

  Central Research Laboratory Hitachi Ltd

• Shima Akio

  Central Research Laboratory Hitachi Ltd.

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