A 100 MHz 7.84 mm^2 31.7 msec 439 mW 512-Point 2-Dimensional FFT Single-Chip Processor(<Special Section>Low-Power System LSI, IP and Related Technologies)
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概要
- 論文の詳細を見る
A single-chip 512-point FFT processor is presented. This processor is based on the cached-memory architecture (CMA) with the resource-saving multi-datapath radix-2^3 computation element. The 2-stage CMA, including a pair of single-port SRAMs, is also introduced to speedup the execution time of the 2-dimensional FFTs. Using the above techniques, we have designed an FFT processor core which integrates 552,000 transistors within an area of 2.8 × 2.8 mm^2 with CMOS 0.35 μm triple-layer-metal process. This processor can execute a 512-point, 36-bit-complex fixed-point data format, 1-dimensonal FFT in 23.2μsec and a 2-dimensional one in only 23.8 msec at 133 MHz operation. The power consumption of this processor is 439.6mW at 3.3V, 100MHz operation.
- 社団法人電子情報通信学会の論文
- 2004-04-01
著者
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Kotani Koji
Graduate School Of Engineering Tohoku University
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OHMI Tadahiro
New Industry Creation Hatchery Center, Tohoku University
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Maruo K
Advantest Laboratories Ltd.
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Maruo Kazuyuki
Advantest Laboratories Ltd.
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Ohmi Tadahiro
New Industry Creation Hatchery Center Future Information Industry Creation Center Tohoku University
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Miyamoto Naoto
Graduate School Of Engineering Tohoku University
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KARNA Leo
Graduate School of Engineering, Tohoku University
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Karna Leo
Graduate School Of Engineering Tohoku University
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Ohmi Tadahiro
New Industry Creation Hatchery Center(niche) Tohoku University
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Ohmi Tadahiro
New Industry Creation Hatchery Center (niche) Tohoku University
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