New Structure of Polycrystalline Silicon Thin-Film Transistor with Germanium Layer in Source/Drain Regions for Low-Temperature Device Fabrication
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概要
- 論文の詳細を見る
We have proposed a new thin-film transistor (TFT) structure in which the activation temperature of implanted dopants in source/drain regions can be reduced to 475 °C. The structure has Ge layers on the source and drain regions; the Ge layers have a role in reducing the activation temperature. The proposed TFTs have shown good drain current–voltage characteristics even though the implanted dopant activation in the source/drain regions has been carried out at 475 °C.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2008-03-25
著者
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YAMANAKA Junji
Center for Crystal Science and Technology, University of Yamanashi
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NAKAGAWA Kiyokazu
Center for Crystal Science and Technology, University of Yamanashi
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Sawano Kentarou
Research Center For Silicon Nano-science Advanced Research Laboratories Musashi Institute Of Technol
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Arimoto Keisuke
Center For Crystal Science And Technology University Of Yamanashi
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Shiraki Yasuhiro
Research Center For Advanced Science And Technology (rcast) The University Of Tokyo
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Sawano Kentarou
Research Center for Silicon Nano-Science, Advanced Research Laboratories, Musashi Institute of Technology, Tokyo 158-0082, Japan
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Mitsui Minoru
Center for Crystal Science and Technology, Faculty of Engineering, University of Yamanashi, Kofu 400-8511, Japan
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Shiraki Yasuhiro
Research Center for Silicon Nano-Science, Advanced Research Laboratories, Musashi Institute of Technology, Tokyo 158-0082, Japan
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Yamanaka Junji
Center for Crystal Science and Technology, Faculty of Engineering, University of Yamanashi, Kofu 400-8511, Japan
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Nakagawa Kiyokazu
Center for Crystal Science and Technology, Faculty of Engineering, University of Yamanashi, Kofu 400-8511, Japan
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