Proposal of a Single-Transistor-Cell-Type Ferroelectric Memory Using an SOI Structure and Experimental Study on the Interference Problem in the Write Operation
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概要
- 論文の詳細を見る
A single-transistor-cell-type ferroelectric random access memory (FRAM) which consists of an array of metal-ferroelectric-semiconductor field effect transistors (MFSFETs) is proposed. In order to minimize the interference problem in the "write/read" operation, use of a silicon-on-insulator (SOI) structure is proposed, as well as optimizing the write and read methods partly using experimental results for ferroelectric capacitors. A key method for avoiding the interference problem is to generate a compensation pulse with a 1/3 amplitude and opposite polarity in the next timing to each write pulse. It is concluded from these considerations that the proposed structure is promising for use as a single-transistor-cell-type FRAM, if the electrical properties of a ferroelectric film on a Si substrate is as good as that on a Pt electrode.
- 社団法人応用物理学会の論文
- 1997-03-30
著者
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TOKUMITSU Eisuke
Precision and Intelligence Laboratory, Tokyo Institute of Technology
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Ishiwara Hiroshi
Graduate School Of Science And Engineering Tokyo Institute Of Technology
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Ishiwara Hiroshi
Tokyo Institute Of Technology Interdisciplinary Graduate School Of Science And Engineering
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Ishiwara Hiroshi
Precision & Intelligence Laboratory Tokyo Institute Of Technology
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Ishiwara Hiroshi
Precision & Intelligence Laboratory Tokyo Institute Of Technology:frontier Collaborative Researc
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Ishiwara H
Tokyo Institute Of Technology Interdisciplinary Graduate School Of Science And Engineering
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Shimamura Toshishige
Precision And Intelligence Laboratory Tokyo Institute Of Technology
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Tokumitsu E
Tokyo Inst. Technol. Yokohama Jpn
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Tokumitsu E
Department Of Electrical And Electronic Engineering Tokyo Institute Of Technology
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Tokumitsu Eisuke
Precision And Intelligence Laboratory Tokyo Institute Of Technology
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Tokumitsu Eisuke
Precision & Intelligence Laboratory, Tokyo Institute of Technology,
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