Electrical Properties of Metal-Ferroelectric-Insulator-Semiconductor (MFIS)- and Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS)-FETs Using Ferroelectric SrBi2Ta2O9 Film and SrTa2O6/SiON Buffer Layer
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概要
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Nonvolatile memory operations of p-channel metal-ferroelctric-insulator-semiconductor (MFIS)- and metal-ferroelectric-metal-insulator-semiconductor (MFMIS)-FETs using ferroelectric SrBi2Ta2O9 (SBT) film and SrTa2O6(STA)/SiON stacked buffer layer have been demonstrated. It is determinded that the Al/STA/SiON/Si structure with a SiO2 equivalent thickness of 3.7 nm has low leakage current of $10^{-8}$ A/cm2. The memory window of 1.1 V is obtained for Pt/SBT/STA/SiON MFIS-FETs, whereas Pt/SBT/Pt/STA/SiON/Si MFMIS-FETs have memory windows as large as 3.0 V when the area ratio $S_{\text{M}}/S_{\text{F}}$ is 3.8 or 5.9. Furthermore, it is also demonstrated that by reducing the metal-ferroelectric-metal (MFM) capacitor area, significant improvement of data retention characteristics can be achieved. The drain current on-off ratio remains at more than three orders of magnitude even after an elapse of 10 h.
- 2000-04-30
著者
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Ishiwara Hiroshi
Precision & Intelligence Laboratory Tokyo Institute Of Technology
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Fujii Gen
Frontier Collaborative Research Center Tokyo Institute Of Technology
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Tokumitsu Eisuke
Precision & Intelligence Laboratory, Tokyo Institute of Technology,
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Ishiwara Hiroshi
Precision & Intelligence Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
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