Generalized Interconnect Delay Time and Crosstalk Models: I. Applications of Interconnect Optimization Design : Semiconductors
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概要
- 論文の詳細を見る
- 社団法人応用物理学会の論文
- 2001-12-15
著者
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Chen H‐c
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University
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Cheng H‐c
National Tsing Hua Univ. Hsinchu Twn
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Cheng Huang‐chung
Nano Electronics And Display Technology Lab. Department Of Electronics Engineering And Institute Of
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Wong S‐c
Taiwan Semiconductor Manufacturing Co. Hsinchu Twn
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Tseng T‐y
National Chiao Tung Univ. Hsinchu Twn
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Tseng Tseung-yuen
Department Of Electronics Engineering National Chiao Tung University
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CHENG Huang-Chung
Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University
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Liang M
Taiwan Semiconductor Manufacturing Corp. Hsinchu Twn
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Liang Mong
Taiwan Semiconductor Manufacturing Corporaton
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Liang Mong
Taiwan Semiconductor Manufacturing Company
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Lee Trent
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University
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Wong Shyh-chyi
Taiwan Semiconductor Manufacturing Company
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Yang Cheng-jer
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tung University
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Cheng Huang-chung
Department Of Electronics Engineering And Institute Of Electronics National Chiao Tang University
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Tseng Tseung-yuen
Department Of Electronics Engineering & Institute Of Electronics National Chiao-tang University
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