Compact Expressions for Crosstalk of Multiple Bit Lines in DRAM
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概要
- 論文の詳細を見る
- 2000-08-28
著者
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Wong Shyh-chyi
Taiwan Semiconductor Manufacturing Company
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LIN Hongchin
Dept. of Electrical Engineering, National Chung-Hsing University
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Lin Hongchin
Dept. Of Electrical Engineering National Chung-hsing University
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Wong Shyh-chyi
Taiwan Semiconductor Manufacturing Corp.
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LAI Yun-Tso
Dept. of Electrical Engineering, National Chung-Hsing University
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Lai Yun-tso
Dept. Of Electrical Engineering National Chung-hsing University
関連論文
- Generalized Interconnect Delay Time and Crosstalk Models: II. Crosstalk-Induced Delay Time Deterioration and Worst Crosstalk Models : Semiconductors
- Generalized Interconnect Delay Time and Crosstalk Models: I. Applications of Interconnect Optimization Design : Semiconductors
- A New Dual Floating Gate Flash Cell for Multilevel Operation
- An Analytical Delay Model for Read Operation at Any Position on DRAM Bit Lines
- Compact Expressions for Crosstalk of Multiple Bit Lines in DRAM
- A New Dual Floating Gate Flash Cell for Multilevel Operation