A New Dual Floating Gate Flash Cell for Multilevel Operation

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概要

• 論文の詳細を見る
• Publication Office, Japanese Journal of Applied Physics, Faculty of Science, University of Tokyoの論文
• 2001-04-01

著者

• Wong S‐c

  Taiwan Semiconductor Manufacturing Co. Hsinchu Twn

• Chen Jack

  Department Of Electrical Engineering National Chung-hsing University

• Wong Shyh-chyi

  Taiwan Semiconductor Manufacturing Company

• LIN Hongchin

  Department of Electrical Engineering, National Chung-Hsing University

関連論文

• Generalized Interconnect Delay Time and Crosstalk Models: II. Crosstalk-Induced Delay Time Deterioration and Worst Crosstalk Models : Semiconductors
• Generalized Interconnect Delay Time and Crosstalk Models: I. Applications of Interconnect Optimization Design : Semiconductors
• A New Dual Floating Gate Flash Cell for Multilevel Operation
• A New Dual Floating Gate Flash Cell for Multilevel Operation
• An Analytical Delay Model for Read Operation at Any Position on Dyamic Random Access Memory Bit Lines
• An Analytical Delay Model for Read Operation at Any Position on DRAM Bit Lines
• Compact Expressions for Crosstalk of Multiple Bit Lines in DRAM
• A New Dual Floating Gate Flash Cell for Multilevel Operation

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