Reliability of Structurally Modified Ultra-Thin Gate Oxides
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概要
- 論文の詳細を見る
- 1995-08-21
著者
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Yasuda Naoki
Mirai-aset Aist
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Toriumi Akira
Mirai-advanced Semiconductor Research Center (mirai-asrc) National Institute Of Advanced Industrial
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Toriumi Akira
Ulsi Research Laboratories Toshiba Corporation
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Toriumi Akira
Ulsi Research Center Toshiba Corporation
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Yasuda Naoki
Advanced Lsi Technology Laboratory Research & Development Center Toshiba Co.
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SATAKE Hideki
ULSI Research Laboratories, TOSHIBA Corporation
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YASUDA Naoki
ULSI Research Laboratories, TOSHIBA Corporation
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SATAKE Hideki
MIRAI, Association of Super-Advanced Electronics Technologies (ASET)
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Toriumi Akira
Advanced Lsi Technology Laboratory Research & Development Center Toshiba Co.
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Satake Hideki
Mirai Association Of Super-advanced Electronics Technologies (aset)
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Satake Hideki
Mirai-aset Aist
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Toriumi Akira
Mirai-advanced Semiconductor Research Center (mirai-asrc) National Institute Of Advanced Industrial
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SATAKE Hideki
ULSI Research Center, TOSHIBA CORPORATION
関連論文
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- Ge/GeO_2 Interface Control with High-Pressure Oxidation for Improving Electrical Characteristics
- Mobility Variations in Mono- and Multi-Layer Graphene Films
- Low Temperature Phosphorus Activation in Germanium through Nickel Germanidation for Shallow n^+/p Junction
- A Significant Shift of Schottky Barrier Heights at Strongly Pinned Metal/Germanium Interface by Inserting an Ultra-Thin Insulating Film
- Grain Size Increase and Field-Effect Mobility Enhancement of Pentacene Thin Films Prepared in a Low-Pressure H_2 Ambient
- Evidence of Electron Trapping Center at Pentacene/SiO_2 Interface
- Origin of Structural Phase Transformation of SiO_2-doped HfO_2
- Advanced Characterization of High-k Gate Stack by Internal Photo Emission (IPE) : Interfacial Dipole and Band Diagram in Al/Hf(Si)O_2/Si MOS Structure
- Effect of Ultra-thin Al_2O_3 Insertion on Fermi-level Pinning at Metal/Ge Interface
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- Direct Evidence of GeO Volatilization from GeO_2 Films and Impact of Its Suppression on GeO_2/Ge MIS Characteristics
- Reduction of Bias-Induced Threshold Voltage Shift in Pentacene Field Effect Transistors by Interface Modification and Molecular Ordering
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