The Role of a Resist During O2 Plasma Ashing and Its Impact on the Reliability Evaluation of Ultrathin Gate Oxides

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概要

• 論文の詳細を見る

• Resists are regarded as protective layers for underlying devices during plasma ashing. In previous studies, resists were deliberately removed by a wet etching process prior to plasma exposure in an effort to achieve significant device degradation. In this paper we report that, contrary to conventional belief, devices with a resist overlayer actually suffer from more severe degradation than those without a resist covering. This resist-enhanced degradation effect, although not observed for devices with a thick gate oxide of 8 nm, becomes significant as the oxide thickness is scaled down below 6 nm. The most severe device degradation is found to be located at the center of the wafer and is found to increase with increasing antenna area ratio. Damage is also found to occur not during the overashing period, but primarily during the initial ashing stage when the resist is still on the electrodes. Using a combination of a simple equivalent capacitor circuit model and the self-adjustment behavior of potential between the wafer surface and substrate, good correlation with the experimental results is obtained.

• Publication Office, Japanese Journal of Applied Physics, Faculty of Science, University of Tokyoの論文
• 1997-07-30

著者

• TSENG Hua-Chou

  Institute of Electronics, National Chiao Tung University

• CHIOU Shean-Guang

  National Nano Device Laboratories

• Huang Tiao-yuan

  Institute Of Electronics National Chiao Tung University

• Chang Tsai-fu

  Institute Of Electronics National Chiao Tung University

• Hsien Szu-kang

  Institute Of Electronics National Chiao Tung University

• Chang Chun-yen

  Institute Of Electronics National Chiao Tang University:national Nano-device Laboratories

• Chien Chao-hsin

  Institute Of Electronics National Chiao-tung University

• Lin Horng-chih

  National Chiao Tung University

• Chang Tsai-Fu

  Institute of Electronics, National Chiao Tung University,

• Huang Tiao-Yuan

  Institute of Electronics, National Chiao Tung University,

• Chiou Shean-Guang

  National Nano Device Laboratories, Hsinchu, Taiwan, R.O.C.

• Tseng Hua-Chou

  Institute of Electronics, National Chiao Tung University,

• Chien Chao-Hsin

  Institute of Electronics, National Chiao Tung University,

• Hsien Szu-Kang

  Institute of Electronics, National Chiao Tung University,

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