Ge p- and n-MOSFETの高電界領域での移動度劣化機構の解析と原子層平坦GeO_x/Ge界面による移動度の向上(IEDM特集(先端CMOSテバイス・プロセス技術))

概要

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Hall measurements have been carried out for the Ge p- and n-MOSFETs with different substrate orientations and GeOx/Ge interface qualities It is found that the significant reduction of effective mobility in high surface carrier concentration (Ns) or high normal field in Ge MOSFETs is attributed partly to the Ns loss due to large amounts of interface states inside the valence and conduction bands of Ge The GeO_x/Ge interface roughness is another reason limiting the high Ns mobility It has been revealed that room temperature plasma post oxidation can realize Al_2O_3/GeO_x/Ge gate stacks with atomically-flat GeOx/Ge interfaces Ge MOSFETs with these interfaces have provided record high effective hole and electron mobility, which overcome the S1 universal mobility in both low and high N_5 regions.
2013-01-23