Numerical Model of Thin-Film Transistors for Circuit Simulation Using Spline Interpolation with Transformation by y=x + log(x)(Regular Section)

概要

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A numerical model of thin-film transistors for circuit simulation has been developed. This model utilizes three schemes. First, the spline interpolation with transformation by y=x + log(x) achieves excellent preciseness for both on-current and off-current simultaneously. Second, the square polynomial supplement solves an anomaly near the points where drain voltage equal to zero. Third, the linear extrapolation achieves continuities of the current and its derivatives as a function of voltages out of the area where the spline interpolation is performed, and improves convergence during circuit simulation.
社団法人電子情報通信学会の論文
2003-01-01