Device Simulation of grain Boundaries with Oxide-Silicon Interface Roughness in Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors
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概要
- 論文の詳細を見る
- 社団法人応用物理学会の論文
- 2000-08-01
著者
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木村 睦
龍谷大学電子情報学科
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井上 聡
セイコーエプソン株式会社フロンティアデバイス研究所
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下田 達也
Center For Nano Materials And Technology Japan Advanced Institute Of Science And Technology
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KIMURA Mutsumi
Ryukoku University
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SHIMODA Tatsuya
Seiko Epson Corporation
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INOUE Satoshi
Base Technology Research Center, Seiko Epson Corp.
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SHIMODA Tatsuya
Base Technology Research Center, Seiko Epson Corp.
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KIMURA Mutsumi
Base Technology Research Center, Seiko Epson Corporation
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Kimura Mutsumi
Ryukoku University:innovative Materials And Processing Research Center
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Shimoda Tatsuya
Base Technology Research Center Seiko Epson Corporation
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Shimoda Tatsuya[
Base Technology Research Center Seiko Epson Corporation
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Kimura M
Department Of Electrical Engineering Kure National College Of Technology
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EGUCHI Tsukasa
LT Business Development Center, Seiko Epson Corporation
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Eguchi Tsukasa
Lt Business Development Center Seiko Epson Corporation
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Kimura Mutsumi
Base Technology Research Center Seiko Epson Corporation
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Kimura Mutsumi
Ryukoku Univ. Otsu‐shi Jpn
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下田 達也
Seiko Epson Corporation
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