Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary in Polycrystalline Silicon Thin-Film Transistors
スポンサーリンク
概要
- 論文の詳細を見る
A technique to extract trap states at the oxide-silicon interface and grain boundary has been developed for polycrystalline silicon thin-film transistors with large grains. From the capacitance–voltage characteristic, the interface traps can be extracted. The potential and carrier density are also extracted. From the potential, carrier density and current–voltage characteristic, the boundary traps can be extracted by considering the potential barrier at the grain boundary. Using a two-dimensional device simulation, the adequacy of this extraction technique was confirmed.
- 2001-01-15
著者
-
INOUE Satoshi
Base Technology Research Center, Seiko Epson Corp.
-
LUI Basil
Epson Cambrodge Laboratory
-
TAM Simon
Epson Cambridge Laboratory
-
Nozawa Ryoichi
Base Technology Research Center Seiko Epson Corporation
-
Migliorato Piero
Department Of Engineering University Of Cambridge
-
Shimoda Tatsuya
Base Technology Research Center Seiko Epson Corporation
-
Kimura Mutsumi
Base Technology Research Center Seiko Epson Corporation
-
Tam Simon
Epson Cambridge Laboratory, 8c King's Parade, Cambridge CB2 1SJ, United Kingdom
-
Migliorato Piero
Department of Engineering, University of Cambridge, Trumpington Street, Cambridge CB2 1PZ, United Kingdom
-
Lui Basil
Epson Cambridge Laboratory, 8c King's Parade, Cambridge CB2 1SJ, United Kingdom
関連論文
- 多結晶シリコン薄膜トランジスタの絶縁膜-シリコン界面と結晶粒界のトラップ準位の抽出(低温または高温多結晶Siとアクティブマトリックス型ディスプレイ用薄膜トランジスタ論文特集)
- Low-Temperature Formation of Device-Quality SiO_2/Si Interfaces Using Electron Cyclotron Resonance Plasma-Enhanced Chemical Vapor Deposition
- Extraction of Trap State at the Oxide-Silicon Interface and Grain Biundary in Polycrystallune Silicon Thin-Film Transistors
- Device Simulation of Grain Boundaries in Lightly Doped Polysilicon Films and Analysis of Dependence on Defect Density
- 低温多結晶シリコン薄膜トランジスタ駆動発光ポリマーディスプレイ
- Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary for Polycrystalline Silicon Thin-Film Transistors : Semiconductors
- Current Density Enhancement at Active Layer Edges in Polycrystalline Silicon Thin-Film Transistors : Semiconductors
- Relationship between Lattice Deformation and Polarization in BaTiO_3
- Electronic States of Perovskite-Type Oxides and Ferroelectricity
- Device Simulation of Carrier Transport through Grain Boundaries in Lightly Doped Polysilicon Films and Dependence on Dopant Density : Semiconductors
- Current Paths over Grain Boundaries in Polycrystalline Silicon Films : Semiconductors
- Selective Deposition of Electroless Plating Films Using the Difference between the Functional Groups of Self-Assembled Monolayers
- Studies of Switching Kinetics in Ferroelectric Thin Films
- Device Simulation of grain Boundaries with Oxide-Silicon Interface Roughness in Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors
- 24.4:Investigation of Hot Carrier Degradation Due to AC Stress in Low Temperature Poly-Si TFTs(発表概要)(Report on 2000 SID International Symposium)
- Pseudo-Lattice Method for Dynamic 3-D Liquid-Crystal Director Simulation
- Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary in Polycrystalline Silicon Thin-Film Transistors
- Studies of Switching Kinetics in Ferroelectric Thin Films
- Device Simulation of Grain Boundaries in Lightly Doped Polysilicon Films and Analysis of Dependence on Defect Density