Pseudo-Lattice Method for Dynamic 3-D Liquid-Crystal Director Simulation

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概要

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• The pseudo-lattice method has been developed for dynamic 3-D liquid-crystal director simulation in thin-film-transistor liquid-crystal displays. Its feature is that the equation of motion of the director is not formularized from the real-lattices, but from the pseudo-lattices organized between the real-lattices. The director on the pseudo-lattice is calculated from the real-lattices by insertion. The objective is to simulate the continuous nematic symmetry correctly and to reduce time and memory needed for the calculation. Especially in this paper, the pseudo-lattice method is explained in detail. Moreover, experiments have been done, and the simulated behavior and location of the bright line, which is caused by the distortion of the director profile, were confirmed to be the same as the actual ones. In particular, the movement and elimination process of the bright line were simulated for the first time.

• 社団法人電子情報通信学会の論文
• 2000-03-25

著者

• INOUE Satoshi

  Base Technology Research Center, Seiko Epson Corp.

• KIMURA Mutsumi

  Base Technology Research Center, Seiko Epson Corporation

• Kimura Mutsumi

  Base Technology Research Center Seiko Epson Corporation

• OZAWA Tokuro

  L Project, Seiko Epson Corporation

• Ozawa Tokuro

  L Project Seiko Epson Corporation

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• Device Simulation of Grain Boundaries in Lightly Doped Polysilicon Films and Analysis of Dependence on Defect Density
• Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary for Polycrystalline Silicon Thin-Film Transistors : Semiconductors
• Current Density Enhancement at Active Layer Edges in Polycrystalline Silicon Thin-Film Transistors : Semiconductors
• Device Simulation of Carrier Transport through Grain Boundaries in Lightly Doped Polysilicon Films and Dependence on Dopant Density : Semiconductors
• Current Paths over Grain Boundaries in Polycrystalline Silicon Films : Semiconductors
• Device Simulation of grain Boundaries with Oxide-Silicon Interface Roughness in Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors
• 24.4:Investigation of Hot Carrier Degradation Due to AC Stress in Low Temperature Poly-Si TFTs(発表概要)(Report on 2000 SID International Symposium)
• Pseudo-Lattice Method for Dynamic 3-D Liquid-Crystal Director Simulation
• Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary in Polycrystalline Silicon Thin-Film Transistors
• Device Simulation of Grain Boundaries in Lightly Doped Polysilicon Films and Analysis of Dependence on Defect Density

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