Device Simulation of Grain Boundaries in Lightly Doped Polysilicon Films and Analysis of Dependence on Defect Density
スポンサーリンク
概要
- 論文の詳細を見る
Device simulations of grain boundaries in lightly doped polysilicon films have been performed. Dependence of the energy band, carrier density, potential barrier and electric conductivity on the defect density and grain size was carefully investigated. As a result, the mechanism of the carrier transportation has been clarified. The boundary defects not only trap and reduce free carriers, but also form the potential barrier and interfere with the carrier movement. As the defect density increases, in the case of the small grain size, first, the space-charge regions spread over the entire grain. Next, while the potential barrier remains the same, the lowest energy of the conduction band from the Fermi level ($E_{\text{c}}$-$E_{\text{f}}$) increases, and the carrier density decreases. Finally, $E_{\text{c}}$-$E_{\text{f}}$ becomes the highest and remains the same. On the other hand, in the case of the large grain size, before the space-charge regions spread over the entire grain, $E_{\text{c}}$-$E_{\text{f}}$ at the grain boundary reaches its maximum. Therefore, even if the defect density increases further, the potential barrier remains the same, and the carrier density remains high. By comparing the experimental and simulated electric conductivity, the defect density can be extracted.
- Publication Office, Japanese Journal of Applied Physics, Faculty of Science, University of Tokyoの論文
- 2001-01-15
著者
-
INOUE Satoshi
Base Technology Research Center, Seiko Epson Corp.
-
SAMESHIMA Toshiyuki
Division of Electric and Information Engineering, Tokyo University of Agriculture and Technology
-
Shimoda Tatsuya
Base Technology Research Center Seiko Epson Corporation
-
Kimura Mutsumi
Base Technology Research Center Seiko Epson Corporation
-
Kimura Mutsumi
Base Technology Research Center, Seiko Epson Corporation, 281 Fujimi, Nagano 399-0293, Japan
-
Shimoda Tatsuya
Base Technology Research Center, Seiko Epson Corporation, 281 Fujimi, Nagano 399-0293, Japan
関連論文
- Low-Temperature Formation of Device-Quality SiO_2/Si Interfaces Using Electron Cyclotron Resonance Plasma-Enhanced Chemical Vapor Deposition
- Extraction of Trap State at the Oxide-Silicon Interface and Grain Biundary in Polycrystallune Silicon Thin-Film Transistors
- Device Simulation of Grain Boundaries in Lightly Doped Polysilicon Films and Analysis of Dependence on Defect Density
- Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary for Polycrystalline Silicon Thin-Film Transistors : Semiconductors
- Current Density Enhancement at Active Layer Edges in Polycrystalline Silicon Thin-Film Transistors : Semiconductors
- Relationship between Lattice Deformation and Polarization in BaTiO_3
- Electronic States of Perovskite-Type Oxides and Ferroelectricity
- Device Simulation of Carrier Transport through Grain Boundaries in Lightly Doped Polysilicon Films and Dependence on Dopant Density : Semiconductors
- Current Paths over Grain Boundaries in Polycrystalline Silicon Films : Semiconductors
- Selective Deposition of Electroless Plating Films Using the Difference between the Functional Groups of Self-Assembled Monolayers
- Device Simulation of grain Boundaries with Oxide-Silicon Interface Roughness in Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors
- 24.4:Investigation of Hot Carrier Degradation Due to AC Stress in Low Temperature Poly-Si TFTs(発表概要)(Report on 2000 SID International Symposium)
- Pseudo-Lattice Method for Dynamic 3-D Liquid-Crystal Director Simulation
- Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary in Polycrystalline Silicon Thin-Film Transistors
- Device Simulation of Grain Boundaries in Lightly Doped Polysilicon Films and Analysis of Dependence on Defect Density