Preparation of Novel PZTN Thin Film Co-doped Si
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概要
- 論文の詳細を見る
- 2004-09-15
著者
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SHIMODA Tatsuya
Seiko Epson Corporation
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Shimoda T
Center For Nano Materials And Technology Japan Advanced Institute Of Science And Technology
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Shimoda Tatsuya
Seiko Epson Corporation Technology Platform Research Center
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KIJIMA Takeshi
Technology Platform Research Center, SEIKO EPSON CORPORATION
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AOYAMA Taku
Technology Platform Research Center, SEIKO EPSON CORPORATION
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HAMADA Yasuaki
Technology Platform Research Center, SEIKO EPSON CORPORATION
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NATORI Eiji
Technology Platform Research Center, SEIKO EPSON CORPORATION
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KIJIMA Takeshi
SEIKO EPSON Corporation, Technology Platform Research Center
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HAMADA Yasuaki
SEIKO EPSON Corporation, Technology Platform Research Center
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AOYAMA Taku
SEIKO EPSON Corporation, Technology Platform Research Center
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NATORI Eiji
SEIKO EPSON Corporation, Technology Platform Research Center
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Shimoda Tatsuya
Seiko Epson Corp. Nagano Jpn
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Aoyama Taku
Technology Platform Research Center Seiko Epson Corporation
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Natori Eiji
Seiko Epson Corporation Technology Platform Research Center
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Kijima T
Functional Devices Laboratories Sharp Corporation
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Kijima Takeshi
Technology Platform Research Center Seiko Epson Corporation
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Hamada Yasuaki
Seiko Epson Corporation Technology Platform Research Center
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Kijima Takeshi
Functional Devices Laboratories Sharp Corporaton
関連論文
- High-Performance Polyclystalline Silicon Thin-Film Transistors with Low Trap Density at the Gate-SiO2/Si Interface Fabricated by Low-Temperature Process
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- High Performance P-Channel Single-Crystalline Si TFTs Fabricated Inside a Location-Controlled Grain by μ-Czochralski Process(Electronic Displays)
- 表側と裏側の絶縁膜界面にトラップ準位をもつポリシリコン薄膜トランジスタのデバイスシミュレーション(ディスプレイ-IDW'03関連-)
- Extraction of Trap Densities at Front and Back Interfaces in Thin-Film Transistors
- Poly-Si TFT特性の酸化膜界面トラップと結晶粒界トラップに対する依存性およびその製造プロセス診断への応用(半導体Si及び関連材料・評価)
- High-Quality Gate-SiO_x and SiO_x/Si Interface Formation at Low Temperature Using Plasma-Enhanced Chemical Vapor Deposition
- Numerical Model of Thin-Film Transistors for Circuit Simulation Using Spline Interpolation with Transformation by y=x + log(x)(Regular Section)
- 多結晶シリコン薄膜トランジスタの絶縁膜-シリコン界面と結晶粒界のトラップ準位の抽出(低温または高温多結晶Siとアクティブマトリックス型ディスプレイ用薄膜トランジスタ論文特集)
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- Plasma Oxidation of Silicon and Its Application to Poly-Si TFT Fabrication Process (情報ディスプレイ--The 6th Asian Symposium on Information Display & Exhibition)
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- Device Simulation of grain Boundaries with Oxide-Silicon Interface Roughness in Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors
- 24.4:Investigation of Hot Carrier Degradation Due to AC Stress in Low Temperature Poly-Si TFTs(発表概要)(Report on 2000 SID International Symposium)
- New Low-Temperature Processing of Metalorganic Chemical Vapor Deposition-Bi_4Ti_3O_ Thin Films Using BiO_x Buffer Layer
- New Low Temperature Processing of MOCVD-Bi_4Ti_3O_ Thin Films Using BiO_x Buffer Layer
- Dry Thermal Oxidation of Polycrystalline and Amorphous Silicon Films for Application to Thin Film Transistors
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- Fabrication and Characterization of Pt/(Bi, La)_4Ti_3O_/Si_3N_4/Si Metal Ferroelectric Insulator Semiconductor Structure for FET-Type Ferroelectric Memory Applications
- Fabrication and Characterization of Pt/(Bi, La)_4Ti_3O_/Si_3N_4/Si MFIS Structure for FET-Type Ferroelectric Memory Applications
- Preparation of Bi_4Ti_3O_ Thin Film on Si(100) Substrate Using Bi_2SiO_5 Buffer Layer and Its Electric Characterization
- Capping Layer on Thin Si Film for $\mu$-Czochralski Process with Excimer Laser Crystallization
- Evaluation of Imprint Property of (111)-Highly Oriented Lead Zirconate Titanate (PZT)-Base Ferroelectric Material
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