Novel Si Codoped Pb(Zr, Ti, Nb)O_3 Thin Film for High-Density Ferroelectric Random Access Memory
スポンサーリンク
概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2005-01-15
著者
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SHIMODA Tatsuya
Technology Platform Research Center, Seiko Epson Cooperation
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Shimoda Tatsuya
Seiko Epson Corporation Technology Platform Research Center
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KIJIMA Takeshi
Technology Platform Research Center, SEIKO EPSON CORPORATION
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AOYAMA Taku
Technology Platform Research Center, SEIKO EPSON CORPORATION
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MIYAZAWA Hiromu
Technology Platform Research Center, SEIKO EPSON CORPORATION
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HAMADA Yasuaki
Technology Platform Research Center, SEIKO EPSON CORPORATION
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OHASHI Koji
Technology Platform Research Center, SEIKO EPSON CORPORATION
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NAKAYAMA Masao
Technology Platform Research Center, SEIKO EPSON CORPORATION
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NATORI Eiji
Technology Platform Research Center, SEIKO EPSON CORPORATION
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Shimoda Tatsuya
Seiko Epson Corp. Nagano Jpn
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Shimoda Tatsuya
Technology Platform Research Center Seiko Epson Corp.
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Ohashi Koji
Technology Platform Research Center Seiko Epson Corporation
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Aoyama Taku
Technology Platform Research Center Seiko Epson Corporation
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Natori Eiji
Seiko Epson Corporation Technology Platform Research Center
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Nakayama Masao
Technology Platform Research Center Seiko Epson Corporation
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Kijima T
Functional Devices Laboratories Sharp Corporation
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Kijima Takeshi
Technology Platform Research Center Seiko Epson Corporation
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Miyazawa H
Base Technology Research Center Seiko Epson Corporation
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Hamada Yasuaki
Seiko Epson Corporation Technology Platform Research Center
関連論文
- High-Performance Polyclystalline Silicon Thin-Film Transistors with Low Trap Density at the Gate-SiO2/Si Interface Fabricated by Low-Temperature Process
- Classification of Driving Methods for TFT-OLEDs and Novel Proposal Using Time Ratio Grayscale and Current Uniformization(Electronic Displays)
- High Performance P-Channel Single-Crystalline Si TFTs Fabricated Inside a Location-Controlled Grain by μ-Czochralski Process(Electronic Displays)
- 表側と裏側の絶縁膜界面にトラップ準位をもつポリシリコン薄膜トランジスタのデバイスシミュレーション(ディスプレイ-IDW'03関連-)
- Extraction of Trap Densities at Front and Back Interfaces in Thin-Film Transistors
- High-Quality Gate-SiO_x and SiO_x/Si Interface Formation at Low Temperature Using Plasma-Enhanced Chemical Vapor Deposition
- Numerical Model of Thin-Film Transistors for Circuit Simulation Using Spline Interpolation with Transformation by y=x + log(x)(Regular Section)
- Low-Temperature Formation of Device-Quality SiO_2/Si Interfaces Using Electron Cyclotron Resonance Plasma-Enhanced Chemical Vapor Deposition
- Extraction of Trap State at the Oxide-Silicon Interface and Grain Biundary in Polycrystallune Silicon Thin-Film Transistors
- Device Simulation of Grain Boundaries in Lightly Doped Polysilicon Films and Analysis of Dependence on Defect Density