High-Performance Polycrystalline Silicon Thin-Film Transistors with Low Trap Density at the Gate-SiO2/Si Interface Fabricated by Low-Temperature Process

概要

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High-performance polycrystalline silicon thin-film transistors with a low trap density at the gate-SiO2/Si interface have been developed using a low-temperature process. It was found that high-performance thin-film transistors with a very low subthreshold swing could be achieved by applying postmetallization annealing at the end of the transistor fabrication. The subthreshold swing and electron mobility of the transistors were 143 mV/dec and 262 cm2 V-1 s-1, respectively, when the thickness of the gate-SiO2 was 114 nm. The ability to fabricate such high-performance thin-film transistors on a glass substrate will be very useful for realizing system-on-panel devices.
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2006-12-15