Extraction Technique of Trap Density at Grain Boundaries in Polycrystalline-Silicon Thin-Film Transistors with Device Simulation
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2007-03-30
著者
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木村 睦
龍谷大学電子情報学科
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井上 聡
セイコーエプソン株式会社フロンティアデバイス研究所
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下田 達也
Center For Nano Materials And Technology Japan Advanced Institute Of Science And Technology
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木村 睦
Department Of Electronics And Informatics Ryukoku University
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HARADA Kiyoshi
Department of Electronics and Informatics, Ryukoku University
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YOSHINO Takuto
Department of Electronics and Informatics, Ryukoku University
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YASUHARA Tohru
Department of Electronics and Informatics, Ryukoku University
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KIMURA Mutsumi
Department of Electronics and Informatics, Ryukoku University
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ABE Daisuke
Frontier Device Research Center, Seiko Epson Corporation
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INOUE Satoshi
Frontier Device Research Center, Seiko Epson Corporation
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SHIMODA Tatsuya
Center for Nano Materials and Technology, Japan Advanced Institute of Science and Technology
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Abe Daisuke
Frontier Device Research Center Seiko Epson Corporation
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Kimura Mutsumi
Ryukoku University:innovative Materials And Processing Research Center
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Yasuhara Tohru
Department Of Electronics And Informatics Ryukoku University
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Yoshino Takuto
Department Of Electronics And Informatics Ryukoku University
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Inoue S
Seiko Epson Corporation
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