Abe Daisuke | Frontier Device Research Center Seiko Epson Corporation

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著作論文

Extraction Technique of Trap Density at Grain Boundaries in Polycrystalline-Silicon Thin-Film Transistors with Device Simulation
High-Performance Polyclystalline Silicon Thin-Film Transistors with Low Trap Density at the Gate-SiO2/Si Interface Fabricated by Low-Temperature Process
High Performance P-Channel Single-Crystalline Si TFTs Fabricated Inside a Location-Controlled Grain by μ-Czochralski Process(Electronic Displays)
表側と裏側の絶縁膜界面にトラップ準位をもつポリシリコン薄膜トランジスタのデバイスシミュレーション(ディスプレイ-IDW'03関連-)
High-Quality Gate-SiO_x and SiO_x/Si Interface Formation at Low Temperature Using Plasma-Enhanced Chemical Vapor Deposition
Low-Temperature Formation of Device-Quality SiO_2/Si Interfaces Using Electron Cyclotron Resonance Plasma-Enhanced Chemical Vapor Deposition
High-Quality SiO_2/Si Interface Formation and Its Application to Fabrication of Low-Temperature-Processed Polycrystalline Si Thin-Film Transistor(Semiconductors)
Extraction Technique of Trap Density at Grain Boundaries in Polycrystalline-Silicon Thin-Film Transistors with Device Simulation

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