IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates(Special Issue on Test and Verification of VLSI)

概要

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In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic values change from L to H by applying a test input vector to a circuit under test. The technique is applied to built-in I_<DDQ> sensor design and external I_<DDQ> sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.
社団法人電子情報通信学会の論文
2002-10-01