An Analysis of the Relationship between IDDQ Testability and D-Type Flip-Flop Structure
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概要
- 論文の詳細を見る
This paper describes IDDQ testability for bridging faults in a variety of flip-flops. The flip-flop is a basic element of the sequential circuit and there are various structures even for the same type. In this paper, we use five kinds of master-slave D-type flip-flops as the circuit under test. Target faults are two-line resistive bridging faults extracted from a circuit layout. A flip-flop with a deliberately introduced bridging fault is simulated by the SPICE simulator. Simulation results show that IDDQ testing cannot detect faults existing at specific points in some flip-flops, and this problem depends on the flip-flop structure. However, IDDQ testing has high fault coverage (≧98%) compared with traditional logic testing. We also examine performances of fully IDDQ testable flip-flops.
- 一般社団法人電子情報通信学会の論文
- 1998-10-25
著者
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Miura Yukiya
Graduate Course Of Electrical Engineering Tokyo Metropolitan University
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Yamazaki Hiroshi
Graduate Course Of Electrical Engineering Tokyo Metropolitan University
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