Synthesis of Testable Sequential Circuits with Reduced Checking Sequences (Special Issue on VLSI Testing and Testable Design)
スポンサーリンク
概要
- 論文の詳細を見る
The test pattern generation for sequential circuits is more difficult than that for combinational circuits due to the presence of memory elements. Therefore we proposed a method for synthesizing sequential circuits with testability in the level of state transition table. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. In this case the checking sequence which do a complete verification of the circuit can be test pattern. The checking sequence have been impractical due to the longer checking sequence required. However, in this paper, we have discussed the condition to reduce the length of checking sequence, then by using suitable state assignment codes sequential circuits with much shorter checking sequences can be realized. A heuristic algorithm of the state assignment which reduce the length of checking sequence is proposed and the algorithm and reduced checking sequence are presented with simple example. The state assignment is very simple with the state matrix which represents the state transition. Furthermore some experimental results of automated synthesis for the MCNC Logic Synthesis Workshop finite state machine benchmark set have shown that the state assignment procedure is efficient for reducing checking sequences.
- 社団法人電子情報通信学会の論文
- 1993-07-25
著者
-
Kinoshita Kozo
Faculty Of Informatics Osaka Gakuin University
-
Kinoshita Kozo
Faculty Of Engineering Osaka University
-
Shibatani Satoshi
Asic Design Engineering Center, Mitsubishi Electric Corporation
-
Shibatani S
Manufacturing Technology Division Semiconductor Group Mitsubishi Electric Corporation
-
Shibatani Satoshi
Asic Design Engineering Center Mitsubishi Electric Corporation
関連論文
- Throughput Analysis of ARQ Schemes in Dialogue Communication over Half-Duplex Line
- Traffic Analysis of the Stop-and-Wait ARQ over a Markov Error Channel
- Channel-Grouping Methods on Go-Back-N ARQ Scheme in Multiple-Parallel-Channel System
- A Novel ATPG Method for Capture Power Reduction during Scan Testing(Dependable Computing)
- A Per-Test Fault Diagnosis Method Based on the X-Fault Model(Dependable Computing)
- A New Method for Low-Capture-Power Test Generation for Scan Testing(Dependable Computing)
- On Design for I_-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies(Computer Components)
- Testing Core-Based System-on-a-Chip Designs
- Transistor Leakage Fault Diagnosis for CMOS Circuits(Special Issue on Test and Diagnosis of VLSI)
- Transistor Leakage Fault Diagnosis with I_DDQ and Logic Information
- Testing of k-FR Circuits under Highly Observable Condition
- Efficient Methods for Guided-Probe Diagnosis (Special Issue on VLSI Testing and Testable Design)
- Synthesis of Testable Sequential Circuits with Reduced Checking Sequences (Special Issue on VLSI Testing and Testable Design)
- Reduction of the Target Fault List and Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino Circuits(Special Issue on Test and Verification of VLSI)
- IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates(Special Issue on Test and Verification of VLSI)
- A Reduced Scan Shift Method for Sequential Circuit Testing (Special Section on VLSI Design and CAD Algorithms)
- A New Rip-Up and Reroute Algorithm for Very Large Scale Gate Arrays (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
- Throughput Performances of ARQ Protocols Operating over Generalized Two-State Markov Error Channel
- Efficient Guided-Probe Fault Location Method for Sequential Circuits
- Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis
- Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement