A Reduced Scan Shift Method for Sequential Circuit Testing (Special Section on VLSI Design and CAD Algorithms)
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概要
- 論文の詳細を見る
This paper presents a method, called reduced scan shift, which generates short test sequences for full scan circuits. In this method, scan shift operations can be reduced, i.e., not all but part of flip-flops (FFs) are controlled and observed. This method, unlike partial scan methods, does not decrease fault coverage. In the reduced scan shift, test vectors for the combinational part of a circuit are firstly generated. Since short test sequence will be obtained from the small test vectors set, test compaction techniques are used in the test vector generation. For each test vector in the obtained test set, it is found which FFs should be controlled or observed. And then a scan chain is configured so that FFs more frequently required to be controlled (observed) can be located close to the scan input (output). After the scan chain is configured, the scan shift requirement is examined for the essential faults of each test vector. Essential fault is defined to be a fault which is detected by only one test vector but not other test vectors. The order of test vectors is carefully determined by comparing the scan control requirement of a test vector with the scan observation requirement of another test vector so that unnecessary scan shift operations only for controlling or observing FFs can be reduced. A method of determining the order of test vectors with state transition is additionally described. The effectiveness of the proposed method is shown by the experimental results for benchmark circuits.
- 社団法人電子情報通信学会の論文
- 1994-12-25
著者
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Kawano K
Okayama Univ. Okayama‐shi Jpn
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Kawano K
Information Technology Center Okayama University
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Kinoshita K
Department Of Information Networking Graduate School Of Information Science And Technology Osaka Uni
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Kinoshita Kozo
Osaka Gakuin University
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Kinoshita Kozo
Faculty Of Engineering Osaka University
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Kajihara Seiji
Faculty Of Computer Science And Systems Engineering Kyushu Institute Of Technology
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Higami Y
Graduate School Of Science And Engineering Ehime University
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Higami Yoshinobu
Faculty of Engineering, Osaka University
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