On Finding Don't Cares in Test Sequences for Sequential Circuits(Dependable Computing)

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概要

• 論文の詳細を見る

• Recently there are various requirements for LSI testing, such as test compaction, test compression, low power dissipation or increase of defect coverage. If test sequences contain lots of don't cares (Xs), then their flexibility can be used to meet the above requirements. In this paper, we propose methods for finding as many Xs as possible in test sequences for sequential circuits. Given a fully specified test sequence generated by a sequential ATPG, the proposed methods produce a test sequence containing Xs without losing stuck-at fault coverage of the original test sequence. The methods apply an approach based on fault simulation, and they introduce some heuristics for reducing the simulation effort. Experimental results for ISCAS'89 benchmark circuits show the effectiveness of the proposed methods.

• 社団法人電子情報通信学会の論文
• 2006-11-01

著者

• KAJIHARA Seiji

  Department of Computer Science and Electronics of Kyushu Institute of Technology

• Kobayashi S

  Graduate School Of Science And Engineering Ehime University

• Kajihara Seiji

  Department Of Computer Sciences And Electronics Kyushu Institute Of Technology

• Takamatsu Y

  Graduate School Of Science And Engineering Ehime University

• Takamatsu Yuzo

  Department Of Electrical And Electronic Engineering And Computer Science Graduate School Of Science

• HIGAMI Yoshinobu

  Department of Computer Science, Ehime University

• POMERANZ Irith

  School of Electrical and Computer Engineering, Purdue University

• KOBAYASHI Shin-ya

  Department of Computer Science, Ehime University

• Higami Y

  Graduate School Of Science And Engineering Ehime University

• Pomeranz Irith

  School Of Electrical And Computer Engineering Purdue University

• Kadoyama Shuhei

  Graduate School Of Science And Engineering Ehime University

• Takamatsu Yuzo

  Department of Computer Science, Ehime University

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• FOREWORD
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• Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools
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• Generation of Test Sequences with Low Power Dissipation for Sequential Circuits(Test Generation and Compaction)(Test and Verification of VLSI)
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• An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation
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