Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool
スポンサーリンク
概要
- 論文の詳細を見る
- 2012-04-01
著者
-
Aikyo Takashi
Department Of Electrical And Electronic Engineering And Computer Science Graduate School Of Science
-
AIKYO Takashi
STARC
-
Higami Y
Graduate School Of Science And Engineering Ehime University
-
Takahashi H
Graduate School Of Science And Engineering Ehime University
-
Shimizu Yoshihiro
Starc (semiconductor Technology Academic Research Center)
-
HIGAMI Yoshinobu
the Graduate School of Science and Engineering, Ehime University
-
OHNO Satoshi
the Graduate School of Science and Engineering, Ehime University
-
YAMAOKA Hironori
the Graduate School of Science and Engineering, Ehime University
-
TAKAHASHI Hiroshi
the Graduate School of Science and Engineering, Ehime University
-
Yamaoka Hironori
The Graduate School Of Science And Engineering Ehime University
-
Ohno Satoshi
The Graduate School Of Science And Engineering Ehime University
関連論文
- A 100 MIPS High Speed and Low Power Digital Signal Processor (Special Issue on Low-Power and High-Speed LSI Technologies)
- A 1.5 V, 200 MHz, 400 MIPS, 188μA/MHz and 1.2 V, 300 MHz, 600 MIPS, 169μA/MHz Digital Signal Processor Core for 3G Wireless Applications(Low-Power System LSI, IP and Related Technologies)
- High-Speed and Low-Power Techniques of Hardware and Software for Digital Signal Processors
- A Circuit Library for Low Power and High Speed Digital Signal Processor
- Fabrication and Characterization of InGaAs/InAlAs Insulated Gate Pseudomorphic HENTs Having a Silicon Interface Control Layer
- Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
- Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors
- Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools
- On Finding Don't Cares in Test Sequences for Sequential Circuits(Dependable Computing)
- Generation of Test Sequences with Low Power Dissipation for Sequential Circuits(Test Generation and Compaction)(Test and Verification of VLSI)
- Problems and Solutions on IDDQ Testing
- Post-BIST Fault Diagnosis for Multiple Faults
- Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
- A Study of Capture-Safe Test Generation Flow for At-Speed Testing
- An Alternative Test Generation for Path Delay Faults by Using N_i-Detection Test Sets(Test)(Dependable Computing)
- An Alternative Test Generation for Path Delay Faults by Using N_i-Detection Test Sets
- Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation(Special Issue on Test and Verification of VLSI)
- Compaction of Test Vectors for IDDQ Testing of Sequential Circuits
- A Reduced Scan Shift Method for Sequential Circuit Testing (Special Section on VLSI Design and CAD Algorithms)
- Test Sequence Generation for Sequential Circuits with Distinguishing Sequences (Special Section on VLSI Design and CAD Algorithms)
- A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects
- Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing
- Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool