A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects

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概要

• 論文の詳細を見る

• Some undetectable stuck-at faults called the redundant faults are included in practical combinational circuits. The redundant fault does not affect the functional behavior of the circuit even if it exists. The redundant fault, however, causes undesirable effects to the circuit such as increase of delay time and decrease of testability of the circuit. It is considered that some redundant faults may cause the logical defects in the future. In this paper, firstly, we study the testability of the redundant fault in the combinational circuit by using delay effects. Secondly, we propose a method for generating a test-pair of a redundant fault by using an extended seven-valued calculus, called TGRF (Test-pair Generation for Redundant Fault). TGRF generates a dynamically sensitizable path for the target line which propagates the change in the value on the target line to a primary output. Finally, we show experimental results on the benchmark circuits under the assumptions of the unit delay and the fanout weighted delay models. It shows that test-pairs for some redundant faults are generated theoretically.

• 社団法人電子情報通信学会の論文
• 1995-07-25

著者

• Takahasi Hiroshi

  The Authors Are With Application Specific Products Worldwide Development Dsp Development Japan Tsuku

• Takamatsu Yuzo

  Faculty Of Engineering Ehime University

• TAKAHASHI Hiroshi

  Faculty of Fisheries, Hokkaido University

• Takahashi H

  Graduate School Of Science And Engineering Ehime University

• Yu Xiangqiu

  Faculty of Engineering, Ehime University

• Yu Xiangqiu

  Faculty Of Engineering Ehime University

• Takahashi Hiroshi

  Faculty Of Engineering Ehime University

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