Generation of Test Sequences with Low Power Dissipation for Sequential Circuits(Test Generation and Compaction)(<Special Section>Test and Verification of VLSI)

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概要

• 論文の詳細を見る

• When LSIs that are designed and manufactured for low power dissipation are tested, test vectors that make the power dissipation low should be applied. If test vectors that cause high power dissipation are applied, incorrect test results are obtained or circuits under test are permanently damaged. In this paper, we propose a method to generate test sequences with low power dissipation for sequential circuits. We assume test sequences generated by an ATPG tool are given, and modify them while keeping the original stuck-at fault coverages. The test sequence is modified by inverting the values of primary inputs of every test vector one by one. In order to keep the original fault coverage, fault simulation is conducted whenever one value of primary inputs is inverted. We introduce heuristics that perform fault simulation for a subset of faults during the modification of test vectors. This helps reduce the power dissipation of the modified test sequence. If the fault coverage by the modified test sequence is lower than that by the original test sequence, we generate a new short test sequence and add it to the modified test sequence.

• 社団法人電子情報通信学会の論文
• 2004-03-01

著者

• Kobayashi S

  Graduate School Of Science And Engineering Ehime University

• Takamatsu Y

  Graduate School Of Science And Engineering Ehime University

• Takamatsu Yuzo

  Department Of Electrical And Electronic Engineering And Computer Science Graduate School Of Science

• HIGAMI Yoshinobu

  Department of Computer Science, Ehime University

• KOBAYASHI Shin-ya

  Department of Computer Science, Ehime University

• Higami Y

  Graduate School Of Science And Engineering Ehime University

• Kadoyama Shuhei

  Graduate School Of Science And Engineering Ehime University

• Takamatsu Yuzo

  Department of Computer Science, Ehime University

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