Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays(Special Issue on Test and Diagnosis of VLSI)

概要

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Testing for delay faults is very important in the verification of the timing behavior of digital circuits. When a circuit which is unable to operate at the desired clock speed is identified, it is necessary to locate the delay fault(s)affecting the circuit in order to remedy the situation. In this paper, we present a path-tracing method of multiple gate delay fault diagnosis in combinational circuits. We first present the basic rules for deducing suspected faults based on the multiple gate delay fault assumption. Next, in order to improve diagnostic resolution, we introduce rules for deducing non-existent faults based on the fault-free responses at the primary outputs. Using these rules, we present the detailed method for diagnosing multiple delay faults based on paths sensitized by test-pairs generated for marginal delays and gate delay faults[7]. Finally, we present results obtained from experiments on the ISCAS'85 benchmark circuits. The experimental results show the effectiveness of our method.
社団法人電子情報通信学会の論文
1998-07-25