Takamatsu Y | Graduate School Of Science And Engineering Ehime University

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概要

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著作論文

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects
Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools
On Finding Don't Cares in Test Sequences for Sequential Circuits(Dependable Computing)
Generation of Test Sequences with Low Power Dissipation for Sequential Circuits(Test Generation and Compaction)(Test and Verification of VLSI)
Problems and Solutions on IDDQ Testing
Post-BIST Fault Diagnosis for Multiple Faults
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
An Alternative Test Generation for Path Delay Faults by Using N_i-Detection Test Sets(Test)(Dependable Computing)
An Alternative Test Generation for Path Delay Faults by Using N_i-Detection Test Sets
Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation(Special Issue on Test and Verification of VLSI)
Compaction of Test Vectors for IDDQ Testing of Sequential Circuits
Design of C-Testable Modified-Booth Multipliers
Diagnosing Delay Faults in Combinational Circuits under the Ambiguous Delay Model
A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits
A Method of Test Generation for Iterative Logic Arrays (特集:VLSIプロセッサ及び新アーキテクチャLSI技術,一般)
A Method of Test Generation for Iterative Logic Arrays (特集 VLSIプロセッサ及び新アーキテクスチャLSI技術、一般)
A Method of Test Generation for Iterative Logic Arrays (特集:VLSIプロセッサ及び新アーキテクチャLSI技術,一般)
Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays(Special Issue on Test and Diagnosis of VLSI)
Design of C-Testable Modified-Booth Multipliers Under the Stuck-at Fault Model

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