An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation

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概要

• 論文の詳細を見る

• Conventional stuck-at fault model is no longer sufficient to deal with the problems of nanometer geometries in modern Large Scale Integrated Circuits (LSIs). Test and diagnosis for transistor defects are required. In this paper we propose a fault diagnosis method for transistor shorts in combinational and full-scan circuits that are described at gale level design. Since it is difficult to describe the precise behavior of faulty transistors, we define two types of transistor short models by focusing on the output values of the corresponding faulty gate. Some of the salient features of the proposed diagnosis method are 1) it uses only gate-level simulation and does not use transistor-level simulation like SPICE, 2) it uses conventional stuck-at fault simulator yet it is able to handle transistor shorts, thus suitable for large circuits, and 3) it is efficient and accurate. We apply our method to ISCAS benchmark circuits to demonstrate the effectiveness of our method.

著者

• HIGAMI Yoshinobu

  Department of Computer Science, Ehime University

• Saluja Kewal

  Department of Electrical and Computer Engineering, University of Wisconsin - Madison

関連論文

• On Finding Don't Cares in Test Sequences for Sequential Circuits(Dependable Computing)
• Generation of Test Sequences with Low Power Dissipation for Sequential Circuits(Test Generation and Compaction)(Test and Verification of VLSI)
• Post-BIST Fault Diagnosis for Multiple Faults
• Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
• An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation
• Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation(Special Issue on Test and Verification of VLSI)

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