Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device
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概要
- 論文の詳細を見る
- 2012-05-01
著者
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Arita Masashi
Graduate School Of Information Science And Technology Hokkaido Univ.
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Ono Yukinori
NTT Basic Research Laboratories
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Inokawa Hiroshi
Research Institute Of Electronics Shizuoka Univ.
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TAKAHASHI Yasuo
Graduate School of Information Science and Technology, Hokkaido University
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Choi Jung-bum
Physics And Research Institute Of Nanoscience And Technology
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Takahashi Y
Hokkaido Univ. Sapporo‐shi Jpn
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Arita Masashi
Graduate School Of Engineering Hokkaido University
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Inokawa H
Research Institute Of Electronics Shizuoka Univ.
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Takahashi Y
Osaka University
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Fujiwara Akira
NTT Basic Research Laboratories, NTT Corporation
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Jo Mingyu
Graduate School Of Information Science And Technology Hokkaido Univ.
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Fujiwara A
Ntt Corp. Atsugi Jpn
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Takahashi Yasuo
Graduate School Of Information Science And Technology Hokkaido Univ.
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Fujiwara Akira
Ntt Basic Research Laboratories Ntt Corporation
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Takahashi Y
Graduate School Of Information Science And Technology Hokkaido Univ.
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Takahashi Yasuo
The Tokyo Metropolitan Research Laboratory Of Public Health:graduate School Of Nutritional And Envir
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Kato Yuki
Graduate School Of Information Science Nagoya University
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Takahashi Yasuo
Faculty Of Pharmaceutical Sciences Tokyo University Of Science
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JO Mingu
Graduate School of Information Science and Technology, Hokkaido University
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Kato Yuki
Graduate School Of Information Science And Technology Hokkaido University
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Takahashi Yasuo
Graduate School of Engineering, Oita University
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