Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture
スポンサーリンク
概要
- 論文の詳細を見る
High-speed and low-power techniques are described for megabit-class size-configurable CMOS SRAM macro-cells. To shorten the design turn-around-time, the methodology of abutting nine kinds of leaf cells is employed; two-level via-hole programming and the array-address decoder embedded in each control leaf cell present a divided-memory-array structure. A new squashed-memory-cell architecture using trench isolation and stacked-via-holes is proposed to reduce access times and power dissipation. To shorten the time for writing data, per-bitline architecture is proposed, in which every bitline has a personal writing driver. Also, read-out circuitry using a current-sense-type two-stage sense amplifier is designed. The effect of the non-multiplexed bitline scheme for fast read-out is shown in a simulation result. To reduce the noise from the second to first-stage amplifier due to a feedback loop, current paths are separated so as not to cause common impedance. To confirm the techniques described in this paper, a 1-Mb SRAM test chip was fabricated with an advanced 0.35-μm CMOS/bulk process. The SRAM has demonstrated 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power dissipation was obtained at a practical operating frequency of 150-MHz.
- 社団法人電子情報通信学会の論文
- 1999-01-25
著者
-
Inokawa Hiroshi
Research Institute Of Electronics Shizuoka Univ.
-
Ohta Soichi
Ntt Advanced Technology Co. Ltd.
-
Inokawa H
Research Institute Of Electronics Shizuoka Univ.
-
Inokawa Hiroshi
Ntt Electronics Co. Ltd.
-
SHIBATA Nobutaro
NTT System Electronics Laboratories
-
TOKUNAGA Keiichiro
NTT Electronics Co., Ltd.
-
Tokunaga Keiichiro
Ntt Electronics Co. Ltd.
関連論文
- Single-electron transfer in phosphorous-doped Si nanowire FETs
- Time-controlled single-electron transfer in single-gated asymmetric multiple tunnel junction arrays
- Effect of UV/ozone Treatment of Nanogap Electrodes for Molecular Devices
- A Single-Electron-Transistor Logic Gate Family for Binary, Multiple-Valued and Mixed-Mode Logic(New System Paradigms for Integrated Electronics)
- A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter
- A Field-Effect Transistor with a Deposited Graphite Thin Film
- Novel-Functional Single-Electron Devices Using Silicon Nanodot Array
- Fabrication of double-dot single-electron transistor in silicon nanowire
- Novel-Functional Single-Electron Devices Using Silicon Nanodot Array
- Fabrication of double-dot single-electron transistor in silicon nanowire
- Single-Electron-Resolution Electrometer Based on Field-Effect Transistor(Session4B: Emerging Devices II)
- Single-Electron-Resolution Electrometer Based on Field-Effect Transistor(Session4B: Emerging Devices II)
- Capacitive Parameter Extraction for Nanometer-Size Field-Effect Transistors
- Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors(Emerging Devices,Fundamentals and Applications of Advanced Semiconductor Devices)
- Charge-State Control of Phosphorus Donors in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor
- Multifunctional Boolean Logic Using Single-Electron Transistors(New System Paradigms for Integrated Electronics)
- Analysis of Back-Gate Voltage Dependence of Threshold Voltage of Thin Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor and Its Application to Si Single-Electron Transistor
- A Multiple-Valued Logic and Memory With Combined Single-Electron and Metal-Oxide-Semiconductor Transistors
- A Merged Single-Electron Transistor and Metal-Oxide-Semiconductor Transistor Logic for Interface and Multiple-Valued Functions
- Multipeak negative-differential-resistance device by combining single-electron and metal-oxide-semiconductor transistors
- A Merged SET-MOSFET Logic for Interface and Multiple-Valued Functions
- Time-controlled single-electron transfer in single-gated asymmetric multiple tunnel junction arrays
- Time-controlled single-electron transfer in single-gated asymmetric multiple tunnel junction arrays
- Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture
- Electrical Characterization of Terphenyl-Based Molecular Devices
- Current-Sensed SRAM Techniques for Megabit-Class Integration : Progress in Operating Frequency by Using Hidden Writing-Recovery Architecture
- Effect of UV/Ozone Treatment on Nanogap Electrodes for Molecular Devices
- A Switched Virtual-GND Level Technique for Fast and Low Power SRAM's
- Fabrication Method of Sub-100 nm Metal-Oxide-Semiconductor Field-Effect Transistor with Thick Gate Oxide
- Single-Photon Detection by a Simple Silicon-on-Insulator Metal--Oxide--Semiconductor Field-Effect Transistor
- Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device
- Field-Effect Transistor with Deposited Graphite Thin Film