Porous Low-$k$ Impacts on Performance of Advanced LSI Devices with GHz Operations

概要

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The impact of porous low-$k$ films on circuit performance in GHz operation was investigated using high-speed circuits in 65 nm complementary metal oxide semiconductor (CMOS) LSI with 11-layered Cu dual damascene interconnects (DDIs). By introducing new non-porogen-type porous films, such as molecular-pore-stacking (MPS) SiOCH films, local low-$k$/Cu structures (M2–M5) with effective dielectric constants ($K_{\text{eff}}$) of 3.1 and 2.9 were fabricated, and their circuit performances were compared to those with conventional local interconnects with $K_{\text{eff}}=3.4$. The interline capacitance ($C_{\text{int}}$), measured using an LCR meter at ${\sim}100$ kHz, was reduced by 12% from $K_{\text{eff}}=3.4$ to 2.9. NAND-type ring oscillators (ROSCs), which were designed to have ${\sim}1.5$ GHz oscillation, also achieved 12 and 10% reductions in signal delay and power consumption, respectively. A 2 GHz static random access memory (SRAM) with $K_{\text{eff}}=2.9$ provides a 4% reduction in bit-line capacitance (M2), resulting in a 6% decrease in $V_{\text{ddmin}}$, or eventually widening the SRAM operation margin. The porous low-$k$ impact on GHz operation is demonstrated for the first time.
2009-04-25