Analysis of Processing Damage on a Ferroelectric SrBi2Ta2O9 Capacitor for Ferroelectric Random Access Memory Device Fabrication
スポンサーリンク
概要
- 論文の詳細を見る
For Ferroelectric random-access memory (FeRAM) device fabrication, it is important to control the processing ambience, especially the hydrogen in process, due to the reduction of ferroelectric oxides such as SrBi2Ta2O9 (SBT). We investigated processing damage to SBT capacitors during (1) the deposition of a cover film on SBT capacitors, (2) the fabrication of a contact hole by reactive ion etching (RIE), and (3) the photoresist mask removal. The O3-TEOS chemical vapor deposition (CVD) process for the deposition of a cover film causes less damage due to the presence of O3 a strong oxidizer. However, during the fabrication of contact holes in SBT capacitors, the plasma-gas species strongly affect the damage to the SBT capacitors. A less damaging process has been developed as follows: forming the contact hole by RIE with CF4 plasma gas instead of CHF3, and removing the photoresist by exposure to oxygen-radical downflow to eliminate hydrogen regeneration from the photoresist decomposition in the O2 plasma. After the process, the leakage current density and the remanent polarization are kept below $10^{-6}$ A/cm-2 and over 15 $\mu$C/cm2, respectively.
- Publication Office, Japanese Journal of Applied Physics, Faculty of Science, University of Tokyoの論文
- 2001-04-15
著者
-
林 喜宏
日本電気株式会社デバイスプラットフォーム研究所
-
林 喜宏
日本電気株式会社マイクロエレクトロニクス研究所 超高集積回路研究部
-
Matsuki Takeo
System Lsi Operations Unit Nec Corporation
-
HAYASHI Yoshihiro
System Devices Research Laboratories, NEC
-
Kawahara Jun
System Devices Research Laboratories Nec
-
Hayashi Yoshihiro
System Devices Research Laboratories, NEC Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
-
Matsuki Takeo
System LSI Operations Unit, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
-
Kawahara Jun
System Devices and Fundamental Research, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
-
Hayashi Yoshihiro
System Devices Research Laboratories, NEC, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
-
Hayashi Yoshihiro
System Devices and Fundamental Research, NEC Corporation, 1120, Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
関連論文
- 0.1μm ULSI世代の超微細アルミニウム多層配線を実現するAl-CMP技術
- アルミリフロースパッタ埋め込みとCMPによる溝配線形成
- 3. 45nm/32nm世代ULSI対応の最先端配線技術(次世代コンピュータを支える超高速・超高密度インタコネクション技術)
- ランダムテレグラフノイズの包括的理解に向けた新解析手法の提案とその応用(IEDM特集(先端CMOSデバイス・プロセス技術))
- High Performance SiN-MIM Decoupling Capacitors with Surface-smoothed Bottom Electrodes for High-speed MPUs
- Impact of Barrier Metal Sputtering on Low-k SiOCH Films with Various Chemical Structures
- A Metallurgical Prescription Suppressing Stress-induced Voiding (SIV) in Cu lines
- Mechanical Property Control of Low-k Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects
- ユビキタス時代に対応したLSIデバイスの構造変革 : RF特性の及ぼす寄生抵抗・容量の影響(配線・実装技術と関連材料技術)
- 低誘電率絶縁膜材料の進化と最先端ULSI多層配線技術
- Improvement of Uniformity and Reliability of Scaled-Down Cu Interconnects with Carbon-Rich Low-$k$ Films
- Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45nm CMOS Generation(Device,Low-Power, High-Speed LSIs and Related Technologies)
- Precise Taper-Angle-Control of Via Holes for Reliable Scaled-Down Low-$k$/Cu Interconnects
- Porous Low-$k$ Impacts on Performance of Advanced LSI Devices with GHz Operations
- A New Differential-Amplifier-Based Offset-Cancellation Sense Amplifier for Speed-Improvement of High-Density Static Random Access Memories in Scaled-Down Complementary Metal–Oxide–Semiconductor Technology
- Surface Control of Bottom Electrode in Ultra-Thin SiN Metal–Insulator–Metal Decoupling Capacitors for High Speed Processors
- Extrasmall-Area Three-Dimensional Solenoid-Shaped Inductor Integrated into High-Speed Signal Processing Complementary Metal–Oxide–Semiconductor Ultralarge-Scale Integrated Circuits
- A Novel Multilayered Ni–Zn-Ferrite/TaN Film for RF/Mobile Applications
- Mechanical Property Control of Low-$k$ Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects
- Defectless Monolithic Low-$k$/Cu Interconnects Produced by Chemically Controlled Chemical Mechanical Polishing Process with In situ End-Point-Detection Technique
- Microstructure Control of Low-Loss Ni–Zn Ferrite by Low-Temperature Sputtering for On-Chip Magnetic Film
- Effects of the Metallurgical Properties of Upper Cu Film on Stress-Induced Voiding (SIV) in Cu Dual-Damascene Interconnects
- Ultrauniform Chemical Mechanical Polishing (CMP) Using a "Hydro Chuck", Featured by Wafer Mounting on a Quartz Glass Plate with Fully Flat, Water-Supported Surface
- Impact of Barrier Metal Sputtering on Physical and Chemical Damages in Low-$k$ SiOCH Films with Various Hydrocarbon Content
- Analysis of Processing Damage on a Ferroelectric SrBi2Ta2O9 Capacitor for Ferroelectric Random Access Memory Device Fabrication
- A Novel Gate Electrode Structure for Reduction of Gate Resistance of Sub-0.1 μm RF/Mixed-Signal Metal Oxide Semiconductor Field-Effect Transistors