Mechanical Property Control of Low-k Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2004-04-30
著者
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Harada Yoshimichi
Device Platforms Research Labs. Nec.
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OHTAKE Hiroto
System Devices Research Laboratories, NEC
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HAYASHI Yoshihiro
System Devices Research Laboratories, NEC
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SAITO Shinobu
System Devices Research Laboratories, NEC Corporation
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HIJIOKA Ken-ichiro
System Devices Research Laboratories, NEC Corporation
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ITO Fuminori
System Devices Research Laboratories, NEC Corporation
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TAGAMI Masayoshi
System Devices Research Laboratories, NEC Corporation
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HARADA Yoshimichi
System Devices Research Laboratories, NEC Corporation
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TAKEUCHI Tsuneo
System Devices Research Laboratories, NEC Corporation
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Saito Shinobu
System Devices Research Laboratories Nec Corporation
関連論文
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- Impact of Barrier Metal Sputtering on Low-k SiOCH Films with Various Chemical Structures
- A Metallurgical Prescription Suppressing Stress-induced Voiding (SIV) in Cu lines
- Mechanical Property Control of Low-k Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects
- Surface Control of Bottom Electrode in Ultra-Thin SiN Metal–Insulator–Metal Decoupling Capacitors for High Speed Processors
- Mechanical Property Control of Low-$k$ Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects
- Effects of the Metallurgical Properties of Upper Cu Film on Stress-Induced Voiding (SIV) in Cu Dual-Damascene Interconnects
- Analysis of Processing Damage on a Ferroelectric SrBi2Ta2O9 Capacitor for Ferroelectric Random Access Memory Device Fabrication