Precise Taper-Angle-Control of Via Holes for Reliable Scaled-Down Low-$k$/Cu Interconnects

概要

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A highly reliable Cu dual-damascene interconnect (DDI) was developed in a molecular-pore-stack (MPS) SiOCH film ($k = 2.5$) with precise taper angle control at the top and bottom of via holes. The durable MPS film with the carbon-rich composition revealed no reliability deterioration in the time-dependent dielectric breakdown (TDDB) between the 140-nm pitched lines. The stres-induced voiding (SiV) was suppressed completely by precise taper angle control both at the top and bottom of via holes. A shallow-tapered via and a stepped via, in which these top taper angles ($\theta_{\text{top}}$) were greater than 45° while keeping the bottom angle ($\theta_{\text{btm}}$) steep at approximately 90°, improved the SiV reliability referred to a deep-tapered via with $\theta_{\text{btm}}\ll 90$°. Finite element method (FEM) simulation well explains the dependence of SiV reliability on both $\theta_{\text{top}}$ and $\theta_{\text{btm}}$; the increment of $\theta_{\text{top}}$ reduces the stress gradient under the via, while the decrease in $\theta_{\text{btm}}$ enlarges the stress gradient. Namely, the precise taper angle control of both the top and bottom via is very important to improve the SiV reliability, and the shallow-tapered and the stepped vias in the MPS film were confirmed to achieve high endurance against the SiV due to relaxation of the stress gradient under the via.
2010-04-25