LPE Growth and Surface Morphology of In_xGa_<1-x>As_yP_<1-y> (y≤0.01) on (100) GaAs

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概要

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• The effects of the growth conditions (growth time, growth temperature and melt concentration) on the surface morphology of an LPE layer of In_xGa_<1-x>As_yP_<1-y>(y≤0.01) on a (100) GaAs substrate are studied. The change in morphology originates from the relation between the growth temperature (T_g) and the equilibrium saturation temperature (T_s) of the source melt, which is in equilibrium with the quaternary solid but is not in equilibrium with the GaAs substrate. The equilibrium temperature was determined from growth layer thickness data, as well as by analysing the phase diagram. It was found that partial growth of the quaternary layer can take place on GaAs even at T_g>T_s, and this is supported by partial melt-back of the substrate. A mirror-like smooth surface was obtained even if the supersaturation ?T was as low as 1℃.

• 社団法人応用物理学会の論文
• 1984-01-20

著者

• Hiramatsu Kazumasa

  Department of Electrical and Electronic Engineering, Faculty of Engineering, Mie University

• SAWAKI Nobuhiko

  Department of Electronics, School of Engineering, Nagoya University, Chikusa-ku, Nagoya

• Akasaki Isamu

  Department Of Electrical And Electronic Engineering Meijyo University

• Akasaki Isamu

  Department Of Electrical And Electronic Engineering And High-tech Research Center Meijo University

• TOMITA Kazuyoshi

  Department of Surgery and Neurosurgery, Osaka University Medical School

• Tomita Kazuyoshi

  Department Of Applied Pharmacology Kyoto Pharmaceutical University

• Tomita Kazuyoshi

  Department Of Electronics School Of Engineering Nagoya University

• Sawaki Nobuhiko

  Department Of Electronics Faculty Of Engineering Nagoya University

• Hiramatsu Kazumasa

  Division Of Electrical And Electronic Engineering Graduate School Of Engineering Mie University

• Hiramatsu Kazumasa

  Department Of Electrical And Electronic Engineering Faculty Of Engineering Mie University

• Sawaki Nobuhiko

  Department of Electrical and Electronic Engineering, Aichi Institute of Technology, Toyota, Aichi 470-0392, Japan

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