Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD)

スポンサーリンク

概要

• 論文の詳細を見る

• This paper proposes a cell layout synthesis technique to minimize the sensitivity to wiring faults due to spot defects. We modeled the sensitivity to faults on intra-cell routings with consideration to the spot defects size distribution and the end effect of critical areas. The effect of the sensitivity reduction on the yield is also discussed. By using the model as a cost function, we comprehensively generate the minimum width layout of CMOS logic cells and select the optimal layouts. Experimental results show that our technique reduces about 15% of the fault sensitivities compared with the wire-length-minimum layouts for benchmark CMOS logic circuits which have up to 14 transistors.

• 社団法人電子情報通信学会の論文
• 2005-07-01

著者

• 飯塚 剛

  愛媛大学理学部

• Ikeda Makoto

  The Vlsi Design And Education Center The University Of Tokyo

• Ikeda Makoto

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Ikeda Makoto

  Department Of Agricultural Chemistry Tohoku University:(present)section Of Phytochemical Research Ei

• Asada K

  Dept. Of Engineering University Of Tokyo:vlsi Design And Education Center University Of Tokyo

• Asada K

  Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T

• Asada Kunihiro

  Department Of Electronic Engineering School Of Engineering The University Of Tokyo:vlsi Design And E

• Ikeda M

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Asada K

  Department Of Electonics Engineering Graduate School Of Engineering The University Of Tokyo

• Asada Kunihiro

  Department Of Electrical And Electronic Engineering Tokyo University

• Iizuka Tetsuya

  Department Of Electronic Engineering Faculty Of Engineering University Of Tokyo:(present Address) Re

• Ikeda Makoto

  Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T

• Iizuka Tetsuya

  Department Of Electronic Engineering And Vlsi Design And Education Center (vdec) The University Of T

• IIZUKA Tetsuya

  Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo

関連論文

• Fermi Surface Properties of the Enhanced Pauli Paramagnet UAl_3 : Condensed Matter: Electronic Properties, etc.
• Magnetic Properties of a Pressure-induced Superconductor UGe_2
• High-Field Magnetization of USn_3 and UPb_3
• Fermi Surface, Magnetic and Superconducting Properties of LaRhln_5 and CeTIn_5 (T: Co, Rh and Ir)
• Quasi-Two Dimensional Fermi Surface Properties of the Antiferromagnet UNiGa_5 : Condensed Matter: Electronic Properties, etc.
• Magnetic and Thermal Properties of CeIrIn_5 and CeRhIn_5 : Condensed Matter: Electronic Properties, etc.
• Electronic States of the Antiferromagnet UGa_3 : Condensed Matter: Electronic Properties, etc.
• High-field magnetization of USn3 and UPb3
• Magnetic Phase Diagram in UCd_
• Frequency dependence of the acoustic radiation pressure on a solid sphere in water
• The in vitro osteogenetic characteristics of primary osteoblastic cells from a rabbit calvarium
• High-Field Magnetic Phase Transitions in CeP
• Oscillatory High-Field Magnetization in LaP Doped with Ce
• High Field Magnetization of Cr-Dimer Complexes
• High Field Magnetization and the Crystalline Electric Field Scheme of TmAl_3
• Time Difference Amplifier with Robust Gain Using Closed-Loop Control
• Footless Dual-Rail Domino Circuit with Self-Timed Precharge Scheme in SOI Technology
• C-12-67 Digital Substrate Noise Canceling Method using Active Guard Ring
• Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability
• Autonomous di/dt Control of Power Supply for Margin Aware Operation(Electronic Circuits)
• Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
• Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs(Papers Selected from AP-ASIC 2004)
• On-Chip di/dt Detector Circuit(Microelectronic Test Structures)
• Stub vs. Capacitor for Power Supply Noise Reduction(Electronic Circuits)
• Noise Immunity Investigation of Low Power Design Schemes(Electronic Circuits)
• On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function (Signal Integrity and Variability, VLSI Design Technology in the Sub-100nm Era)
• C-12-18 On-chip Detector for Non-Periodic High-Swing Noise Sensing
• A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells(Computer Components)
• A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits(Integrated Electronics)
• A Logic-Cell-Embedded PLA (LCPLA) : An Area-Efficient Dual-Rail Array Logic Architecture(Integrated Electronics)
• Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
• Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
• A-3-7 A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells
• A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers
• 22aVD-2 一般化ダブルサインゴルドン方程式のキンク解及びソリトン解(22aVD 古典・量子可積分系(数値計算アルゴリズムを含む),領域11(統計力学,物性基礎論,応用数学,力学,流体物理))
• ジレンマゲームにおけるダイナミックス(経済物理学II-社会・経済への物理学的アプローチ-,京都大学基礎物理学研究所2005年度後期研究会)
• ジレンマゲームにおけるダイナミックス(経済物理学II-社会・経済への物理学的アプローチ-,京都大学基礎物理学研究所2005年度後期研究会)
• ソニック結晶の非線形波 (非線形波動現象の数理とその応用)
• Gap Solitons in Nonlinear Polyatomic Chains(Condensed Matter : Structure, Mechanical and Thermal Properties)
• Coupled Mode Theory and The Gap Soliton (Mathematical Analysis in Fluid and Gas Dynamics)
• レーリー及びランジュバン放射圧に関する一般理論
• Soliton Scattering by an Object in Nonlinear Media
• Two-Dimensional Wave Propagation in Inhomogeneous Reaction-Diffusion Media
• Grating Solitons in Optical Fiber
• Grating solitonの理論的解析(波動の非線形現象の数理とその応用)
• Gap Soliton と非線形シュレディンガー方程式(波の非線形現象の数理とその応用)
• Envelope Soliton of the Bloch Wave in Nonlinear Periodic Lattices
• 周期系におけるBloch波の包絡ソリトンII(流体の非線形波動現象の数理とその応用)
• Coupled Hybrid Nonlinear Schrodinger Equation and Optical Solitons
• Curve Lengthening Equation and Its Solutions
• 周期系におけるBloch波の包絡ソリトン(流体における波動現象の数理とその応用)
• 不均一系における非線形波動:底の深さが不均一な3次元浅水波(流体における波動現象の数理とその応用)
• A Structural Approach for Transistor Circuit Synthesis(Circuit Synthesis,VLSI Design and CAD Algorithms)
• Pixel-Level Color Demodulation Image Sensor for Support of Image Recognition(Electronic Circuits)
• Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories(New System Paradigms for Integrated Electronics)
• A Row-Parallel Position Detector for High-Speed 3-D Camera Based on Light-Section Method(Electronic Circuits)
• High-Sensitivity and Wide-Dynamic-Range Position Sensor Using Logarithmic-Response and Correlation Circuit
• Wide Dynamic Range Photo Detector for Smart Position Sensor Using Log-Response and Correlation Circuit
• A Synchronous Completion Prediction Adder (SCPA)
• Magnetic and Fermi Surface Properties of UPtGa_5
• Suppression of the Josephson Current in Normal-Distribution-Shaped Tunnel Junctions
• Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells(Circuit Synthesis, VLSI Design and CAD Algorithms)
• Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization(VLSI Design Technology and CAD)
• High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability(Physical Design)(VLSI Design and CAD Algorithms)
• Anomalous High-Field Metamagnetism Based on the Quadrupole Interaction in TmCu2 (Proceedings of the International Conference on Strongly Correlated Electrons with Orbital Degrees of Freedom(ORBITAL2001))
• Non-Approximate Evaluation of Macroscopic Quantum Tunneling of Charge for the Two-Junction Case at Arbitrary Temperatures and Bias Voltages
• Power Optimization for Data Compressors Based on a Window Detector in a 54 × 54 Bit Multiplier
• A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment
• Thiamine requirement of two different cultured cell lines of soybean
• Habituation in suspension-cultured soybean cells to thiamine and its precursors
• The thiamine requirement for callus formation from soybean hypocotyl
• Thiamine requirements of various plant cells in suspension culture
• Calculations of Energy Levels of Oxygen and Silicon Vacancies at the Si-SiO_2 Interface
• Fabrication of Step-Edge Junctions on the Concave or Convex Side of YBa_2Cu_3O_ Film
• Magnetic and Electrical Properties of Vacuum-Deposited CdCr_2Se_4 Thin Film
• Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method
• Sjogren syndrome associated with multiple myeloma of the lgA _k-type
• Fiske Steps of Josephson Tunnel Junctions Formed with Normal-Distribution Functi
• Proposal of a Digital Double Relaxation Oscillation SQUID(Special Issue on Superconductive Electronics)
• Design of High-Speed High-Density Parallel Adders and Multipliers Using Regenerative Pass-Transistor Logic
• A-3-12 A MONTE-CARLO ANALYSIS OF STATIC CMOS AND DUAL-RAIL PLA FOR SUB-100NM PARAMETER VARIATIONS
• Case of a 23-Year-Old Woman with Serous Surface Papilloma of Borderline Malignancy of the Left Ovary and Mucinous Cystadenoma of the Right Ovary
• On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
• Cascaded Time Difference Amplifier with Differential Logic Delay Cell
• All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
• 1.0ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells
• A 580fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18µm CMOS Technology
• On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction
• Thermodynamical Calculation and Experimental Confirmation of the Density of Hole Traps in SiO_2 Films
• High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters
• Cascade Model for Reduction of Field-Effect Mobility of Electrons in Lightly Doped Channel of Submicron Gate Si Thin-Film Field-Effect Transistors
• Two Cases of Refractory Wegeners Granulomatosis Successfully Treated with Rituximab
• Crystallization Mechanism of Poly(l-lactic acid) under DC External Field
• C-2-15 Direct Burst Pulse Generator for Sub-millimeter Wave Integrated on 65-nm CMOS
• Study of cationic surfactant ion selective poly(vinyl chloride) membrane electrode containing dibenzo-18-crown-6.
• C-12-40 Effect of CMOS Device Scaling on Time-domain Voltage-domain Dynamic Range
• A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing

もっと見る 閉じる

スポンサーリンク